arm.isa (7407:70f65d4c7fe3) arm.isa (7418:e81194228b6e)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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76 0x7: Breakpoint::bkpt();
77 }
78 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
79 }
80 }
81 }
82 0x1: decode IS_MISC {
83 0: ArmDataProcImm::armDataProcImm();
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 67 unchanged lines hidden (view full) ---

76 0x7: Breakpoint::bkpt();
77 }
78 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
79 }
80 }
81 }
82 0x1: decode IS_MISC {
83 0: ArmDataProcImm::armDataProcImm();
84 1: decode OPCODE {
85 // The following two instructions aren't supposed to be defined
86 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
87 0x9: decode RN {
88 0: decode IMM {
89 0: PredImmOp::nop({{ ; }});
90#if FULL_SYSTEM
91 1: PredImmOp::yield({{ ; }});
92 2: PredImmOp::wfe({{
93 if (SevMailbox)
94 SevMailbox = 0;
95 else
96 PseudoInst::quiesce(xc->tcBase());
97 }}, IsNonSpeculative, IsQuiesce);
98 3: PredImmOp::wfi({{
99 PseudoInst::quiesce(xc->tcBase());
100 }}, IsNonSpeculative, IsQuiesce);
101 4: PredImmOp::sev({{
102 // Need a way for O3 to not scoreboard these
103 // accesses as pipeflushs
104 System *sys = xc->tcBase()->getSystemPtr();
105 for (int x = 0; x < sys->numContexts(); x++) {
106 ThreadContext *oc = sys->getThreadContext(x);
107 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
108 }
109 }});
110#endif
111 }
112 default: PredImmOp::msr_i_cpsr({{
113 SCTLR sctlr = Sctlr;
114 uint32_t newCpsr =
115 cpsrWriteByInstr(Cpsr | CondCodes,
116 rotated_imm, RN, false, sctlr.nmfi);
117 Cpsr = ~CondCodesMask & newCpsr;
118 CondCodes = CondCodesMask & newCpsr;
119 }});
120 }
121 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
122 0xb: PredImmOp::msr_i_spsr({{
123 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
124 }});
125 }
84 1: ArmMisc::armMisc();
126 }
127 0x2: AddrMode2::addrMode2(True);
128 0x3: decode OPCODE_4 {
129 0: AddrMode2::addrMode2(False);
130 1: decode OPCODE_24_23 {
131 0x0: ArmParallelAddSubtract::armParallelAddSubtract();
132 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
133 0x2: ArmSignedMultiplies::armSignedMultiplies();

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86 0x2: AddrMode2::addrMode2(True);
87 0x3: decode OPCODE_4 {
88 0: AddrMode2::addrMode2(False);
89 1: decode OPCODE_24_23 {
90 0x0: ArmParallelAddSubtract::armParallelAddSubtract();
91 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
92 0x2: ArmSignedMultiplies::armSignedMultiplies();

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