arm.isa (7344:82a4e24e7fad) arm.isa (7350:41e3ee23125e)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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81 0x1: decode IS_MISC {
82 0: ArmDataProcImm::armDataProcImm();
83 1: decode OPCODE {
84 // The following two instructions aren't supposed to be defined
85 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
86 0x9: decode RN {
87 0: decode IMM {
88 0: PredImmOp::nop({{ ; }});
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 72 unchanged lines hidden (view full) ---

81 0x1: decode IS_MISC {
82 0: ArmDataProcImm::armDataProcImm();
83 1: decode OPCODE {
84 // The following two instructions aren't supposed to be defined
85 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
86 0x9: decode RN {
87 0: decode IMM {
88 0: PredImmOp::nop({{ ; }});
89 1: WarnUnimpl::yield();
90 2: WarnUnimpl::wfe();
91 3: WarnUnimpl::wfi();
92 4: WarnUnimpl::sev();
89#if FULL_SYSTEM
90 1: PredImmOp::yield({{ ; }});
91 2: PredImmOp::wfe({{
92 if (SevMailbox)
93 SevMailbox = 0;
94 else
95 PseudoInst::quiesce(xc->tcBase());
96 }}, IsNonSpeculative, IsQuiesce);
97 3: PredImmOp::wfi({{
98 PseudoInst::quiesce(xc->tcBase());
99 }}, IsNonSpeculative, IsQuiesce);
100 4: PredImmOp::sev({{
101 // Need a way for O3 to not scoreboard these
102 // accesses as pipeflushs
103 System *sys = xc->tcBase()->getSystemPtr();
104 for (int x = 0; x < sys->numContexts(); x++) {
105 ThreadContext *oc = sys->getThreadContext(x);
106 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
107 }
108 }});
109#endif
93 }
94 default: PredImmOp::msr_i_cpsr({{
95 uint32_t newCpsr =
96 cpsrWriteByInstr(Cpsr | CondCodes,
97 rotated_imm, RN, false);
98 Cpsr = ~CondCodesMask & newCpsr;
99 CondCodes = CondCodesMask & newCpsr;
100 }});

--- 71 unchanged lines hidden --- 		110 }
111 default: PredImmOp::msr_i_cpsr({{
112 uint32_t newCpsr =
113 cpsrWriteByInstr(Cpsr | CondCodes,
114 rotated_imm, RN, false);
115 Cpsr = ~CondCodesMask & newCpsr;
116 CondCodes = CondCodesMask & newCpsr;
117 }});

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