| arm.isa (7197:21b9790c446d) | arm.isa (7199:3e96b80d1b55) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 272 unchanged lines hidden (view full) --- 281 1: PredOp::mrc_cp15({{ 282 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 283 }}); 284 } 285 } // RN 286 } // CPNUM (OP4 == 1) 287 } //OPCODE_4 288 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 272 unchanged lines hidden (view full) --- 281 1: PredOp::mrc_cp15({{ 282 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 283 }}); 284 } 285 } // RN 286 } // CPNUM (OP4 == 1) 287 } //OPCODE_4 288 |
| 289 1: PredOp::swi({{ 290#if FULL_SYSTEM 291 fault = new SupervisorCall(); 292#else 293 fault = new SupervisorCall(machInst); 294#endif 295 }}, IsSyscall); | 289 1: Svc::svc(); |
| 296 } // OPCODE_24 297 298} 299} 300} 301 | 290 } // OPCODE_24 291 292} 293} 294} 295 |