| arm.isa (7195:ccd270981263) | arm.isa (7197:21b9790c446d) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 272 unchanged lines hidden (view full) --- 281 1: PredOp::mrc_cp15({{ 282 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 283 }}); 284 } 285 } // RN 286 } // CPNUM (OP4 == 1) 287 } //OPCODE_4 288 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 272 unchanged lines hidden (view full) --- 281 1: PredOp::mrc_cp15({{ 282 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 283 }}); 284 } 285 } // RN 286 } // CPNUM (OP4 == 1) 287 } //OPCODE_4 288 |
| 289 1: PredOp::swi({{ |
|
| 289#if FULL_SYSTEM | 290#if FULL_SYSTEM |
| 290 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); | 291 fault = new SupervisorCall(); |
| 291#else | 292#else |
| 292 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode)) 293 { 294 if (IMMED_23_0) 295 xc->syscall(IMMED_23_0); 296 else 297 xc->syscall(R7); 298 } 299 }}); 300#endif // FULL_SYSTEM | 293 fault = new SupervisorCall(machInst); 294#endif 295 }}, IsSyscall); |
| 301 } // OPCODE_24 302 303} 304} 305} 306 | 296 } // OPCODE_24 297 298} 299} 300} 301 |