arm.isa (7152:a1308654b445) arm.isa (7161:a1e9b36bd4bf)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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50//
51//
52
530: decode ENCODING {
54format DataOp {
55 0x0: decode SEVEN_AND_FOUR {
56 1: decode MISC_OPCODE {
57 0x9: decode PREPOST {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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50//
51//
52
530: decode ENCODING {
54format DataOp {
55 0x0: decode SEVEN_AND_FOUR {
56 1: decode MISC_OPCODE {
57 0x9: decode PREPOST {
58 0: decode OPCODE {
59 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
60 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none);
61 0x2: WarnUnimpl::umall();
62 0x4: umull({{
63 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
64 Rd = (uint32_t)(resTemp & 0xffffffff);
65 Rn = (uint32_t)(resTemp >> 32);
66 }}, llbit);
67 0x5: smlal({{
68 resTemp = ((int64_t)Rm) * ((int64_t)Rs);
69 resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd);
70 Rd = (uint32_t)(resTemp & 0xffffffff);
71 Rn = (uint32_t)(resTemp >> 32);
72 }}, llbit);
73 0x6: smull({{
74 resTemp = ((int64_t)(int32_t)Rm)*
75 ((int64_t)(int32_t)Rs);
76 Rd = (int32_t)(resTemp & 0xffffffff);
77 Rn = (int32_t)(resTemp >> 32);
78 }}, llbit);
79 0x7: umlal({{
80 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
81 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
82 Rd = (uint32_t)(resTemp & 0xffffffff);
83 Rn = (uint32_t)(resTemp >> 32);
84 }}, llbit);
85 }
58 0: ArmMultAndMultAcc::armMultAndMultAcc();
86 1: decode PUBWL {
87 0x10: WarnUnimpl::swp();
88 0x14: WarnUnimpl::swpb();
89 0x18: WarnUnimpl::strex();
90 0x19: WarnUnimpl::ldrex();
91 }
92 }
93 0xb, 0xd, 0xf: AddrMode3::addrMode3();
94 }
95 0: decode IS_MISC {
96 0: ArmDataProcReg::armDataProcReg();
59 1: decode PUBWL {
60 0x10: WarnUnimpl::swp();
61 0x14: WarnUnimpl::swpb();
62 0x18: WarnUnimpl::strex();
63 0x19: WarnUnimpl::ldrex();
64 }
65 }
66 0xb, 0xd, 0xf: AddrMode3::addrMode3();
67 }
68 0: decode IS_MISC {
69 0: ArmDataProcReg::armDataProcReg();
97 1: decode MISC_OPCODE {
98 0x0: decode OPCODE {
99 0x8: PredOp::mrs_cpsr({{
100 Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
101 }});
102 0x9: decode USEIMM {
103 // The mask field is the same as the RN index.
104 0: PredOp::msr_cpsr_reg({{
105 uint32_t newCpsr =
106 cpsrWriteByInstr(Cpsr | CondCodes,
107 Rm, RN, false);
108 Cpsr = ~CondCodesMask & newCpsr;
109 CondCodes = CondCodesMask & newCpsr;
70 1: decode OPCODE_7 {
71 0x0: decode MISC_OPCODE {
72 0x0: decode OPCODE {
73 0x8: PredOp::mrs_cpsr({{
74 Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
110 }});
75 }});
111 1: PredImmOp::msr_cpsr_imm({{
112 uint32_t newCpsr =
113 cpsrWriteByInstr(Cpsr | CondCodes,
114 rotated_imm, RN, false);
115 Cpsr = ~CondCodesMask & newCpsr;
116 CondCodes = CondCodesMask & newCpsr;
117 }});
76 0x9: decode USEIMM {
77 // The mask field is the same as the RN index.
78 0: PredOp::msr_cpsr_reg({{
79 uint32_t newCpsr =
80 cpsrWriteByInstr(Cpsr | CondCodes,
81 Rm, RN, false);
82 Cpsr = ~CondCodesMask & newCpsr;
83 CondCodes = CondCodesMask & newCpsr;
84 }});
85 1: PredImmOp::msr_cpsr_imm({{
86 uint32_t newCpsr =
87 cpsrWriteByInstr(Cpsr | CondCodes,
88 rotated_imm, RN, false);
89 Cpsr = ~CondCodesMask & newCpsr;
90 CondCodes = CondCodesMask & newCpsr;
91 }});
92 }
93 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
94 0xb: decode USEIMM {
95 // The mask field is the same as the RN index.
96 0: PredOp::msr_spsr_reg({{
97 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
98 }});
99 1: PredImmOp::msr_spsr_imm({{
100 Spsr = spsrWriteByInstr(Spsr, rotated_imm,
101 RN, false);
102 }});
103 }
118 }
104 }
119 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
120 0xb: decode USEIMM {
121 // The mask field is the same as the RN index.
122 0: PredOp::msr_spsr_reg({{
123 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
105 0x1: decode OPCODE {
106 0x9: ArmBx::armBx();
107 0xb: PredOp::clz({{
108 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
124 }});
109 }});
125 1: PredImmOp::msr_spsr_imm({{
126 Spsr = spsrWriteByInstr(Spsr, rotated_imm,
127 RN, false);
128 }});
129 }
110 }
111 0x2: decode OPCODE {
112 0x9: WarnUnimpl::bxj();
113 }
114 0x3: decode OPCODE {
115 0x9: ArmBlxReg::armBlxReg();
116 }
117 0x5: decode OPCODE {
118 0x8: WarnUnimpl::qadd();
119 0x9: WarnUnimpl::qsub();
120 0xa: WarnUnimpl::qdadd();
121 0xb: WarnUnimpl::qdsub();
122 }
130 }
123 }
131 0x1: decode OPCODE {
132 0x9: ArmBx::armBx();
133 0xb: PredOp::clz({{
134 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
135 }});
136 }
137 0x2: decode OPCODE {
138 0x9: WarnUnimpl::bxj();
139 }
140 0x3: decode OPCODE {
141 0x9: ArmBlxReg::armBlxReg();
142 }
143 0x5: decode OPCODE {
144 0x8: WarnUnimpl::qadd();
145 0x9: WarnUnimpl::qsub();
146 0xa: WarnUnimpl::qdadd();
147 0xb: WarnUnimpl::qdsub();
148 }
149 0x8: decode OPCODE {
150 0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
151 0x9: WarnUnimpl::smlalbb();
152 0xa: WarnUnimpl::smlawb();
153 0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none);
154 }
155 0xa: decode OPCODE {
156 0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
157 0x9: smulwb({{
158 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16);
159 }}, none);
160 0xa: WarnUnimpl::smlaltb();
161 0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none);
162 }
163 0xc: decode OPCODE {
164 0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
165 0x9: WarnUnimpl::smlawt();
166 0xa: WarnUnimpl::smlalbt();
167 0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none);
168 }
169 0xe: decode OPCODE {
170 0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
171 0x9: smulwt({{
172 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16);
173 }}, none);
174 0xa: WarnUnimpl::smlaltt();
175 0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none);
176 }
124 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
177 }
178 }
179 }
180 0x1: decode IS_MISC {
181 0: ArmDataProcImm::armDataProcImm();
182 1: decode OPCODE {
183 // The following two instructions aren't supposed to be defined
184 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});

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202 0xb: PredImmOp::msr_i_spsr({{
203 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
204 }});
205 }
206 }
207 0x2: AddrMode2::addrMode2(True);
208 0x3: decode OPCODE_4 {
209 0: AddrMode2::addrMode2(False);
125 }
126 }
127 }
128 0x1: decode IS_MISC {
129 0: ArmDataProcImm::armDataProcImm();
130 1: decode OPCODE {
131 // The following two instructions aren't supposed to be defined
132 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});

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150 0xb: PredImmOp::msr_i_spsr({{
151 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
152 }});
153 }
154 }
155 0x2: AddrMode2::addrMode2(True);
156 0x3: decode OPCODE_4 {
157 0: AddrMode2::addrMode2(False);
210 1: decode MEDIA_OPCODE {
211 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
212 0x8: decode MISC_OPCODE {
213 0x1, 0x9: WarnUnimpl::pkhbt();
214 0x7: WarnUnimpl::sxtab16();
215 0xb: WarnUnimpl::sel();
216 0x5, 0xd: WarnUnimpl::pkhtb();
217 0x3: WarnUnimpl::sign_zero_extend_add();
218 }
219 0xa, 0xb: decode SHIFT {
220 0x0, 0x2: WarnUnimpl::ssat();
221 0x1: WarnUnimpl::ssat16();
222 }
223 0xe, 0xf: decode SHIFT {
224 0x0, 0x2: WarnUnimpl::usat();
225 0x1: WarnUnimpl::usat16();
226 }
227 0x10: decode RN {
228 0xf: decode MISC_OPCODE {
229 0x1: WarnUnimpl::smuad();
230 0x3: WarnUnimpl::smuadx();
231 0x5: WarnUnimpl::smusd();
232 0x7: WarnUnimpl::smusdx();
158 1: decode OPCODE_24_23 {
159 0x0: WarnUnimpl::parallel_add_subtract_instructions();
160 0x1: decode MEDIA_OPCODE {
161 0x8: decode MISC_OPCODE {
162 0x1, 0x9: WarnUnimpl::pkhbt();
163 0x7: WarnUnimpl::sxtab16();
164 0xb: WarnUnimpl::sel();
165 0x5, 0xd: WarnUnimpl::pkhtb();
166 0x3: WarnUnimpl::sign_zero_extend_add();
233 }
167 }
234 default: decode MISC_OPCODE {
235 0x1: WarnUnimpl::smlad();
236 0x3: WarnUnimpl::smladx();
237 0x5: WarnUnimpl::smlsd();
238 0x7: WarnUnimpl::smlsdx();
168 0xa, 0xb: decode SHIFT {
169 0x0, 0x2: WarnUnimpl::ssat();
170 0x1: WarnUnimpl::ssat16();
239 }
171 }
172 0xe, 0xf: decode SHIFT {
173 0x0, 0x2: WarnUnimpl::usat();
174 0x1: WarnUnimpl::usat16();
175 }
240 }
176 }
241 0x14: decode MISC_OPCODE {
242 0x1: WarnUnimpl::smlald();
243 0x3: WarnUnimpl::smlaldx();
244 0x5: WarnUnimpl::smlsld();
245 0x7: WarnUnimpl::smlsldx();
246 }
247 0x15: decode RN {
248 0xf: decode MISC_OPCODE {
249 0x1: WarnUnimpl::smmul();
250 0x3: WarnUnimpl::smmulr();
177 0x2: ArmSignedMultiplies::armSignedMultiplies();
178 0x3: decode MEDIA_OPCODE {
179 0x18: decode RN {
180 0xf: WarnUnimpl::usada8();
181 default: WarnUnimpl::usad8();
251 }
182 }
252 default: decode MISC_OPCODE {
253 0x1: WarnUnimpl::smmla();
254 0x3: WarnUnimpl::smmlar();
255 0xd: WarnUnimpl::smmls();
256 0xf: WarnUnimpl::smmlsr();
257 }
258 }
183 }
259 0x18: decode RN {
260 0xf: WarnUnimpl::usada8();
261 default: WarnUnimpl::usad8();
262 }
263 }
264 }
265 0x4: ArmMacroMem::armMacroMem();
266 0x5: decode OPCODE_24 {
267 0: ArmBBlxImm::armBBlxImm();
268 1: ArmBlBlxImm::armBlBlxImm();
269 }
270 0x6: decode CPNUM {

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185 }
186 0x4: ArmMacroMem::armMacroMem();
187 0x5: decode OPCODE_24 {
188 0: ArmBBlxImm::armBBlxImm();
189 1: ArmBlBlxImm::armBlBlxImm();
190 }
191 0x6: decode CPNUM {

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