arm.isa (7120:d630089169f3) arm.isa (7129:0eb03024678f)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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85 }
86 1: decode PUBWL {
87 0x10: WarnUnimpl::swp();
88 0x14: WarnUnimpl::swpb();
89 0x18: WarnUnimpl::strex();
90 0x19: WarnUnimpl::ldrex();
91 }
92 }
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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85 }
86 1: decode PUBWL {
87 0x10: WarnUnimpl::swp();
88 0x14: WarnUnimpl::swpb();
89 0x18: WarnUnimpl::strex();
90 0x19: WarnUnimpl::ldrex();
91 }
92 }
93 format AddrMode3 {
94 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }},
95 load, {{ Rd = Mem.uh; }});
96 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0);
97 Rdo = bits(Mem.ud, 63, 32); }},
98 load, {{ Rd = Mem.sb; }});
99 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) |
100 (Rdo.ud << 32); }},
101 load, {{ Rd = Mem.sh; }});
102 }
93 0xb, 0xd, 0xf: AddrMode3::addrMode3();
103 }
104 0: decode IS_MISC {
105 0: decode OPCODE {
106 0x0: and({{ Rd = resTemp = Rn & op2; }});
107 0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
108 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
109 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
110 0x4: add({{ Rd = resTemp = Rn + op2; }}, add);

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95 0: decode IS_MISC {
96 0: decode OPCODE {
97 0x0: and({{ Rd = resTemp = Rn & op2; }});
98 0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
99 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
100 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
101 0x4: add({{ Rd = resTemp = Rn + op2; }}, add);

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