1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
530: decode COND_CODE {
540xF: ArmUnconditional::armUnconditional();
55default: decode ENCODING {
56format DataOp {
57 0x0: decode SEVEN_AND_FOUR {
58 1: decode MISC_OPCODE {
59 0x9: decode PREPOST {
60 0: ArmMultAndMultAcc::armMultAndMultAcc();
61 1: ArmSyncMem::armSyncMem();
62 }
63 0xb, 0xd, 0xf: AddrMode3::addrMode3();
64 }
65 0: decode IS_MISC {
66 0: ArmDataProcReg::armDataProcReg();
67 1: decode OPCODE_7 {
68 0x0: decode MISC_OPCODE {
69 0x0: ArmMsrMrs::armMsrMrs();
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72 0x3: decode OPCODE {
73 0x9: ArmBlxReg::armBlxReg();
74 }
75 0x5: ArmSatAddSub::armSatAddSub();
76 }
77 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
78 }
79 }
80 }
81 0x1: decode IS_MISC {
82 0: ArmDataProcImm::armDataProcImm();
83 1: decode OPCODE {
84 // The following two instructions aren't supposed to be defined
85 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
86 0x9: decode RN {
87 0: decode IMM {
88 0: PredImmOp::nop({{ ; }});
89 1: WarnUnimpl::yield();
90 2: WarnUnimpl::wfe();
91 3: WarnUnimpl::wfi();
92 4: WarnUnimpl::sev();
93 }
94 default: PredImmOp::msr_i_cpsr({{
95 uint32_t newCpsr =
96 cpsrWriteByInstr(Cpsr | CondCodes,
97 rotated_imm, RN, false);
98 Cpsr = ~CondCodesMask & newCpsr;
99 CondCodes = CondCodesMask & newCpsr;
100 }});
101 }
102 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
103 0xb: PredImmOp::msr_i_spsr({{
104 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
105 }});
106 }
107 }
108 0x2: AddrMode2::addrMode2(True);
109 0x3: decode OPCODE_4 {
110 0: AddrMode2::addrMode2(False);
111 1: decode OPCODE_24_23 {
112 0x0: ArmParallelAddSubtract::armParallelAddSubtract();
113 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
114 0x2: ArmSignedMultiplies::armSignedMultiplies();
115 0x3: ArmMiscMedia::armMiscMedia();
116 }
117 }
118 0x4: ArmMacroMem::armMacroMem();
119 0x5: decode OPCODE_24 {
120 0: ArmBBlxImm::armBBlxImm();
121 1: ArmBlBlxImm::armBlBlxImm();
122 }
123 0x6: decode CPNUM {
124 0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStore();
125 }
126 0x7: decode OPCODE_24 {
127 0: decode OPCODE_4 {
128 0: decode CPNUM {
129 0xa, 0xb: decode OPCODE_23_20 {
130##include "vfp.isa"
131 }
132 } // CPNUM
133 1: decode CPNUM { // 27-24=1110,4 ==1
134 1: decode OPCODE_15_12 {
135 format FloatOp {
136 0xf: decode OPCODE_23_21 {
137 format FloatCmp {
138 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
139 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
140 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
141 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
142 }
143 }
144 default: decode OPCODE_23_20 {
145 0x0: decode OPCODE_7 {
146 0: flts({{ Fn.sf = (float) Rd.sw; }});
147 1: fltd({{ Fn.df = (double) Rd.sw; }});
148 }
149 0x1: decode OPCODE_7 {
150 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
151 1: fixd({{ Rd = (uint32_t) Fm.df; }});
152 }
153 0x2: wfs({{ Fpsr = Rd; }});
154 0x3: rfs({{ Rd = Fpsr; }});
155 0x4: FailUnimpl::wfc();
156 0x5: FailUnimpl::rfc();
157 }
158 } // format FloatOp
159 }
160 0xa, 0xb: ShortFpTransfer::shortFpTransfer();
161 0xf: McrMrc15::mcrMrc15();
162 } // CPNUM (OP4 == 1)
163 } //OPCODE_4
164
165 1: Svc::svc();
166 } // OPCODE_24
167
168}
169}
170}
171
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