1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
53decode COND_CODE {
540xF: ArmUnconditional::armUnconditional();
55default: decode ENCODING {
56format DataOp {
57 0x0: decode SEVEN_AND_FOUR {
58 1: decode MISC_OPCODE {
59 0x9: decode PREPOST {
60 0: ArmMultAndMultAcc::armMultAndMultAcc();
61 1: ArmSyncMem::armSyncMem();
62 }
63 0xb, 0xd, 0xf: AddrMode3::addrMode3();
64 }
65 0: decode IS_MISC {
66 0: ArmDataProcReg::armDataProcReg();
67 1: decode OPCODE_7 {
68 0x0: decode MISC_OPCODE {
69 0x0: ArmMsrMrs::armMsrMrs();
70 // bxj unimplemented, treated as bx
71 0x1,0x2: ArmBxClz::armBxClz();
72 0x3: decode OPCODE {
73 0x9: ArmBlxReg::armBlxReg();
74 }
75 0x5: ArmSatAddSub::armSatAddSub();
76 0x7: Breakpoint::bkpt();
77 }
78 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
79 }
80 }
81 }
82 0x1: decode IS_MISC {
83 0: ArmDataProcImm::armDataProcImm();
84 1: ArmMisc::armMisc();
85 }
86 0x2: AddrMode2::addrMode2(True);
87 0x3: decode OPCODE_4 {
88 0: AddrMode2::addrMode2(False);
89 1: decode OPCODE_24_23 {
90 0x0: ArmParallelAddSubtract::armParallelAddSubtract();
91 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
92 0x2: ArmSignedMultiplies::armSignedMultiplies();
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
53decode COND_CODE {
540xF: ArmUnconditional::armUnconditional();
55default: decode ENCODING {
56format DataOp {
57 0x0: decode SEVEN_AND_FOUR {
58 1: decode MISC_OPCODE {
59 0x9: decode PREPOST {
60 0: ArmMultAndMultAcc::armMultAndMultAcc();
61 1: ArmSyncMem::armSyncMem();
62 }
63 0xb, 0xd, 0xf: AddrMode3::addrMode3();
64 }
65 0: decode IS_MISC {
66 0: ArmDataProcReg::armDataProcReg();
67 1: decode OPCODE_7 {
68 0x0: decode MISC_OPCODE {
69 0x0: ArmMsrMrs::armMsrMrs();
70 // bxj unimplemented, treated as bx
71 0x1,0x2: ArmBxClz::armBxClz();
72 0x3: decode OPCODE {
73 0x9: ArmBlxReg::armBlxReg();
74 }
75 0x5: ArmSatAddSub::armSatAddSub();
76 0x7: Breakpoint::bkpt();
77 }
78 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
79 }
80 }
81 }
82 0x1: decode IS_MISC {
83 0: ArmDataProcImm::armDataProcImm();
84 1: ArmMisc::armMisc();
85 }
86 0x2: AddrMode2::addrMode2(True);
87 0x3: decode OPCODE_4 {
88 0: AddrMode2::addrMode2(False);
89 1: decode OPCODE_24_23 {
90 0x0: ArmParallelAddSubtract::armParallelAddSubtract();
91 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
92 0x2: ArmSignedMultiplies::armSignedMultiplies();
|
94 }
95 }
96 0x4: ArmMacroMem::armMacroMem();
97 0x5: decode OPCODE_24 {
98 0: ArmBBlxImm::armBBlxImm();
99 1: ArmBlBlxImm::armBlBlxImm();
100 }
101 0x6: decode CPNUM {
102 0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStore();
103 }
104 0x7: decode OPCODE_24 {
105 0: decode OPCODE_4 {
106 0: decode CPNUM {
107 0xa, 0xb: VfpData::vfpData();
108 } // CPNUM
109 1: decode CPNUM { // 27-24=1110,4 ==1
| 99 }
100 }
101 0x4: ArmMacroMem::armMacroMem();
102 0x5: decode OPCODE_24 {
103 0: ArmBBlxImm::armBBlxImm();
104 1: ArmBlBlxImm::armBlBlxImm();
105 }
106 0x6: decode CPNUM {
107 0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStore();
108 }
109 0x7: decode OPCODE_24 {
110 0: decode OPCODE_4 {
111 0: decode CPNUM {
112 0xa, 0xb: VfpData::vfpData();
113 } // CPNUM
114 1: decode CPNUM { // 27-24=1110,4 ==1
|