1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
530: decode COND_CODE {
540xF: ArmUnconditional::armUnconditional();
55default: decode ENCODING {
56format DataOp {
57 0x0: decode SEVEN_AND_FOUR {
58 1: decode MISC_OPCODE {
59 0x9: decode PREPOST {
60 0: ArmMultAndMultAcc::armMultAndMultAcc();
61 1: ArmSyncMem::armSyncMem();
62 }
63 0xb, 0xd, 0xf: AddrMode3::addrMode3();
64 }
65 0: decode IS_MISC {
66 0: ArmDataProcReg::armDataProcReg();
67 1: decode OPCODE_7 {
68 0x0: decode MISC_OPCODE {
69 0x0: ArmMsrMrs::armMsrMrs();
70 // bxj unimplemented, treated as bx
71 0x1,0x2: ArmBxClz::armBxClz();
72 0x3: decode OPCODE {
73 0x9: ArmBlxReg::armBlxReg();
74 }
75 0x5: ArmSatAddSub::armSatAddSub();
76 }
77 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
78 }
79 }
80 }
81 0x1: decode IS_MISC {
82 0: ArmDataProcImm::armDataProcImm();
83 1: decode OPCODE {
84 // The following two instructions aren't supposed to be defined
85 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
86 0x9: decode RN {
87 0: decode IMM {
88 0: PredImmOp::nop({{ ; }});
89#if FULL_SYSTEM
90 1: PredImmOp::yield({{ ; }});
91 2: PredImmOp::wfe({{
92 if (SevMailbox)
93 SevMailbox = 0;
94 else
95 PseudoInst::quiesce(xc->tcBase());
96 }}, IsNonSpeculative, IsQuiesce);
97 3: PredImmOp::wfi({{
98 PseudoInst::quiesce(xc->tcBase());
99 }}, IsNonSpeculative, IsQuiesce);
100 4: PredImmOp::sev({{
101 // Need a way for O3 to not scoreboard these
102 // accesses as pipeflushs
103 System *sys = xc->tcBase()->getSystemPtr();
104 for (int x = 0; x < sys->numContexts(); x++) {
105 ThreadContext *oc = sys->getThreadContext(x);
106 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
107 }
108 }});
109#endif
110 }
111 default: PredImmOp::msr_i_cpsr({{
112 uint32_t newCpsr =
113 cpsrWriteByInstr(Cpsr | CondCodes,
114 rotated_imm, RN, false);
115 Cpsr = ~CondCodesMask & newCpsr;
116 CondCodes = CondCodesMask & newCpsr;
117 }});
118 }
119 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
120 0xb: PredImmOp::msr_i_spsr({{
121 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
122 }});
123 }
124 }
125 0x2: AddrMode2::addrMode2(True);
126 0x3: decode OPCODE_4 {
127 0: AddrMode2::addrMode2(False);
128 1: decode OPCODE_24_23 {
129 0x0: ArmParallelAddSubtract::armParallelAddSubtract();
130 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
131 0x2: ArmSignedMultiplies::armSignedMultiplies();
132 0x3: ArmMiscMedia::armMiscMedia();
133 }
134 }
135 0x4: ArmMacroMem::armMacroMem();
136 0x5: decode OPCODE_24 {
137 0: ArmBBlxImm::armBBlxImm();
138 1: ArmBlBlxImm::armBlBlxImm();
139 }
140 0x6: decode CPNUM {
141 0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStore();
142 }
143 0x7: decode OPCODE_24 {
144 0: decode OPCODE_4 {
145 0: decode CPNUM {
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
530: decode COND_CODE {
540xF: ArmUnconditional::armUnconditional();
55default: decode ENCODING {
56format DataOp {
57 0x0: decode SEVEN_AND_FOUR {
58 1: decode MISC_OPCODE {
59 0x9: decode PREPOST {
60 0: ArmMultAndMultAcc::armMultAndMultAcc();
61 1: ArmSyncMem::armSyncMem();
62 }
63 0xb, 0xd, 0xf: AddrMode3::addrMode3();
64 }
65 0: decode IS_MISC {
66 0: ArmDataProcReg::armDataProcReg();
67 1: decode OPCODE_7 {
68 0x0: decode MISC_OPCODE {
69 0x0: ArmMsrMrs::armMsrMrs();
70 // bxj unimplemented, treated as bx
71 0x1,0x2: ArmBxClz::armBxClz();
72 0x3: decode OPCODE {
73 0x9: ArmBlxReg::armBlxReg();
74 }
75 0x5: ArmSatAddSub::armSatAddSub();
76 }
77 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
78 }
79 }
80 }
81 0x1: decode IS_MISC {
82 0: ArmDataProcImm::armDataProcImm();
83 1: decode OPCODE {
84 // The following two instructions aren't supposed to be defined
85 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
86 0x9: decode RN {
87 0: decode IMM {
88 0: PredImmOp::nop({{ ; }});
89#if FULL_SYSTEM
90 1: PredImmOp::yield({{ ; }});
91 2: PredImmOp::wfe({{
92 if (SevMailbox)
93 SevMailbox = 0;
94 else
95 PseudoInst::quiesce(xc->tcBase());
96 }}, IsNonSpeculative, IsQuiesce);
97 3: PredImmOp::wfi({{
98 PseudoInst::quiesce(xc->tcBase());
99 }}, IsNonSpeculative, IsQuiesce);
100 4: PredImmOp::sev({{
101 // Need a way for O3 to not scoreboard these
102 // accesses as pipeflushs
103 System *sys = xc->tcBase()->getSystemPtr();
104 for (int x = 0; x < sys->numContexts(); x++) {
105 ThreadContext *oc = sys->getThreadContext(x);
106 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
107 }
108 }});
109#endif
110 }
111 default: PredImmOp::msr_i_cpsr({{
112 uint32_t newCpsr =
113 cpsrWriteByInstr(Cpsr | CondCodes,
114 rotated_imm, RN, false);
115 Cpsr = ~CondCodesMask & newCpsr;
116 CondCodes = CondCodesMask & newCpsr;
117 }});
118 }
119 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
120 0xb: PredImmOp::msr_i_spsr({{
121 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
122 }});
123 }
124 }
125 0x2: AddrMode2::addrMode2(True);
126 0x3: decode OPCODE_4 {
127 0: AddrMode2::addrMode2(False);
128 1: decode OPCODE_24_23 {
129 0x0: ArmParallelAddSubtract::armParallelAddSubtract();
130 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
131 0x2: ArmSignedMultiplies::armSignedMultiplies();
132 0x3: ArmMiscMedia::armMiscMedia();
133 }
134 }
135 0x4: ArmMacroMem::armMacroMem();
136 0x5: decode OPCODE_24 {
137 0: ArmBBlxImm::armBBlxImm();
138 1: ArmBlBlxImm::armBlBlxImm();
139 }
140 0x6: decode CPNUM {
141 0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStore();
142 }
143 0x7: decode OPCODE_24 {
144 0: decode OPCODE_4 {
145 0: decode CPNUM {
|
149 } // CPNUM
150 1: decode CPNUM { // 27-24=1110,4 ==1
151 1: decode OPCODE_15_12 {
152 format FloatOp {
153 0xf: decode OPCODE_23_21 {
154 format FloatCmp {
155 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
156 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
157 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
158 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
159 }
160 }
161 default: decode OPCODE_23_20 {
162 0x0: decode OPCODE_7 {
163 0: flts({{ Fn.sf = (float) Rd.sw; }});
164 1: fltd({{ Fn.df = (double) Rd.sw; }});
165 }
166 0x1: decode OPCODE_7 {
167 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
168 1: fixd({{ Rd = (uint32_t) Fm.df; }});
169 }
170 0x2: wfs({{ Fpsr = Rd; }});
171 0x3: rfs({{ Rd = Fpsr; }});
172 0x4: FailUnimpl::wfc();
173 0x5: FailUnimpl::rfc();
174 }
175 } // format FloatOp
176 }
177 0xa, 0xb: ShortFpTransfer::shortFpTransfer();
178 0xf: McrMrc15::mcrMrc15();
179 } // CPNUM (OP4 == 1)
180 } //OPCODE_4
181
182 1: Svc::svc();
183 } // OPCODE_24
184
185}
186}
187}
188
| 147 } // CPNUM
148 1: decode CPNUM { // 27-24=1110,4 ==1
149 1: decode OPCODE_15_12 {
150 format FloatOp {
151 0xf: decode OPCODE_23_21 {
152 format FloatCmp {
153 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
154 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
155 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
156 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
157 }
158 }
159 default: decode OPCODE_23_20 {
160 0x0: decode OPCODE_7 {
161 0: flts({{ Fn.sf = (float) Rd.sw; }});
162 1: fltd({{ Fn.df = (double) Rd.sw; }});
163 }
164 0x1: decode OPCODE_7 {
165 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
166 1: fixd({{ Rd = (uint32_t) Fm.df; }});
167 }
168 0x2: wfs({{ Fpsr = Rd; }});
169 0x3: rfs({{ Rd = Fpsr; }});
170 0x4: FailUnimpl::wfc();
171 0x5: FailUnimpl::rfc();
172 }
173 } // format FloatOp
174 }
175 0xa, 0xb: ShortFpTransfer::shortFpTransfer();
176 0xf: McrMrc15::mcrMrc15();
177 } // CPNUM (OP4 == 1)
178 } //OPCODE_4
179
180 1: Svc::svc();
181 } // OPCODE_24
182
183}
184}
185}
186
|