1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
530: decode COND_CODE {
540xF: ArmUnconditional::armUnconditional();
55default: decode ENCODING {
56format DataOp {
57 0x0: decode SEVEN_AND_FOUR {
58 1: decode MISC_OPCODE {
59 0x9: decode PREPOST {
60 0: ArmMultAndMultAcc::armMultAndMultAcc();
61 1: ArmSyncMem::armSyncMem();
62 }
63 0xb, 0xd, 0xf: AddrMode3::addrMode3();
64 }
65 0: decode IS_MISC {
66 0: ArmDataProcReg::armDataProcReg();
67 1: decode OPCODE_7 {
68 0x0: decode MISC_OPCODE {
69 0x0: ArmMsrMrs::armMsrMrs();
70 0x1: decode OPCODE {
71 0x9: ArmBx::armBx();
72 0xb: PredOp::clz({{
73 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
74 }});
75 }
76 0x2: decode OPCODE {
77 0x9: WarnUnimpl::bxj();
78 }
79 0x3: decode OPCODE {
80 0x9: ArmBlxReg::armBlxReg();
81 }
82 0x5: ArmSatAddSub::armSatAddSub();
83 }
84 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
85 }
86 }
87 }
88 0x1: decode IS_MISC {
89 0: ArmDataProcImm::armDataProcImm();
90 1: decode OPCODE {
91 // The following two instructions aren't supposed to be defined
92 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
93 0x9: decode RN {
94 0: decode IMM {
95 0: PredImmOp::nop({{ ; }});
96 1: WarnUnimpl::yield();
97 2: WarnUnimpl::wfe();
98 3: WarnUnimpl::wfi();
99 4: WarnUnimpl::sev();
100 }
101 default: PredImmOp::msr_i_cpsr({{
102 uint32_t newCpsr =
103 cpsrWriteByInstr(Cpsr | CondCodes,
104 rotated_imm, RN, false);
105 Cpsr = ~CondCodesMask & newCpsr;
106 CondCodes = CondCodesMask & newCpsr;
107 }});
108 }
109 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
110 0xb: PredImmOp::msr_i_spsr({{
111 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
112 }});
113 }
114 }
115 0x2: AddrMode2::addrMode2(True);
116 0x3: decode OPCODE_4 {
117 0: AddrMode2::addrMode2(False);
118 1: decode OPCODE_24_23 {
119 0x0: ArmParallelAddSubtract::armParallelAddSubtract();
120 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
121 0x2: ArmSignedMultiplies::armSignedMultiplies();
122 0x3: decode MEDIA_OPCODE {
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
530: decode COND_CODE {
540xF: ArmUnconditional::armUnconditional();
55default: decode ENCODING {
56format DataOp {
57 0x0: decode SEVEN_AND_FOUR {
58 1: decode MISC_OPCODE {
59 0x9: decode PREPOST {
60 0: ArmMultAndMultAcc::armMultAndMultAcc();
61 1: ArmSyncMem::armSyncMem();
62 }
63 0xb, 0xd, 0xf: AddrMode3::addrMode3();
64 }
65 0: decode IS_MISC {
66 0: ArmDataProcReg::armDataProcReg();
67 1: decode OPCODE_7 {
68 0x0: decode MISC_OPCODE {
69 0x0: ArmMsrMrs::armMsrMrs();
70 0x1: decode OPCODE {
71 0x9: ArmBx::armBx();
72 0xb: PredOp::clz({{
73 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
74 }});
75 }
76 0x2: decode OPCODE {
77 0x9: WarnUnimpl::bxj();
78 }
79 0x3: decode OPCODE {
80 0x9: ArmBlxReg::armBlxReg();
81 }
82 0x5: ArmSatAddSub::armSatAddSub();
83 }
84 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
85 }
86 }
87 }
88 0x1: decode IS_MISC {
89 0: ArmDataProcImm::armDataProcImm();
90 1: decode OPCODE {
91 // The following two instructions aren't supposed to be defined
92 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
93 0x9: decode RN {
94 0: decode IMM {
95 0: PredImmOp::nop({{ ; }});
96 1: WarnUnimpl::yield();
97 2: WarnUnimpl::wfe();
98 3: WarnUnimpl::wfi();
99 4: WarnUnimpl::sev();
100 }
101 default: PredImmOp::msr_i_cpsr({{
102 uint32_t newCpsr =
103 cpsrWriteByInstr(Cpsr | CondCodes,
104 rotated_imm, RN, false);
105 Cpsr = ~CondCodesMask & newCpsr;
106 CondCodes = CondCodesMask & newCpsr;
107 }});
108 }
109 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
110 0xb: PredImmOp::msr_i_spsr({{
111 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
112 }});
113 }
114 }
115 0x2: AddrMode2::addrMode2(True);
116 0x3: decode OPCODE_4 {
117 0: AddrMode2::addrMode2(False);
118 1: decode OPCODE_24_23 {
119 0x0: ArmParallelAddSubtract::armParallelAddSubtract();
120 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
121 0x2: ArmSignedMultiplies::armSignedMultiplies();
122 0x3: decode MEDIA_OPCODE {
|
127 }
128 }
129 }
130 0x4: ArmMacroMem::armMacroMem();
131 0x5: decode OPCODE_24 {
132 0: ArmBBlxImm::armBBlxImm();
133 1: ArmBlBlxImm::armBlBlxImm();
134 }
135 0x6: decode CPNUM {
136 0xb: ExtensionRegLoadStore::extensionRegLoadStore();
137 }
138 0x7: decode OPCODE_24 {
139 0: decode OPCODE_4 {
140 0: decode CPNUM {
141 0xa, 0xb: decode OPCODE_23_20 {
142##include "vfp.isa"
143 }
144 } // CPNUM
145 1: decode CPNUM { // 27-24=1110,4 ==1
146 1: decode OPCODE_15_12 {
147 format FloatOp {
148 0xf: decode OPCODE_23_21 {
149 format FloatCmp {
150 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
151 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
152 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
153 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
154 }
155 }
156 default: decode OPCODE_23_20 {
157 0x0: decode OPCODE_7 {
158 0: flts({{ Fn.sf = (float) Rd.sw; }});
159 1: fltd({{ Fn.df = (double) Rd.sw; }});
160 }
161 0x1: decode OPCODE_7 {
162 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
163 1: fixd({{ Rd = (uint32_t) Fm.df; }});
164 }
165 0x2: wfs({{ Fpsr = Rd; }});
166 0x3: rfs({{ Rd = Fpsr; }});
167 0x4: FailUnimpl::wfc();
168 0x5: FailUnimpl::rfc();
169 }
170 } // format FloatOp
171 }
172 0xa: decode MISC_OPCODE {
173 0x1: decode MEDIA_OPCODE {
174 0xf: decode RN {
175 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
176 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
177 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
178 }
179 0xe: decode RN {
180 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
181 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
182 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
183 }
184 } // MEDIA_OPCODE (MISC_OPCODE 0x1)
185 } // MISC_OPCODE (CPNUM 0xA)
186 0xf: decode RN {
187 // Barrriers, Cache Maintence, NOPS
188 7: decode OPCODE_23_21 {
189 0: decode RM {
190 0: decode OPC2 {
191 4: decode OPCODE_20 {
192 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
193 }
194 }
195 1: WarnUnimpl::cp15_cache_maint();
196 4: WarnUnimpl::cp15_par();
197 5: decode OPC2 {
198 0,1: WarnUnimpl::cp15_cache_maint2();
199 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
200 6,7: WarnUnimpl::cp15_bp_maint();
201 }
202 6: WarnUnimpl::cp15_cache_maint3();
203 8: WarnUnimpl::cp15_va_to_pa();
204 10: decode OPC2 {
205 1,2: WarnUnimpl::cp15_cache_maint3();
206 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
207 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
208 }
209 11: WarnUnimpl::cp15_cache_maint4();
210 13: decode OPC2 {
211 1: decode OPCODE_20 {
212 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
213 }
214 }
215 14: WarnUnimpl::cp15_cache_maint5();
216 } // RM
217 } // OPCODE_23_21 CR
218
219 // Thread ID and context ID registers
220 // Thread ID register needs cheaper access than miscreg
221 13: WarnUnimpl::mcr_mrc_cp15_c7();
222
223 // All the rest
224 default: decode OPCODE_20 {
225 0: PredOp::mcr_cp15({{
226 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
227 }});
228 1: PredOp::mrc_cp15({{
229 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
230 }});
231 }
232 } // RN
233 } // CPNUM (OP4 == 1)
234 } //OPCODE_4
235
236 1: Svc::svc();
237 } // OPCODE_24
238
239}
240}
241}
242
| 124 }
125 }
126 }
127 0x4: ArmMacroMem::armMacroMem();
128 0x5: decode OPCODE_24 {
129 0: ArmBBlxImm::armBBlxImm();
130 1: ArmBlBlxImm::armBlBlxImm();
131 }
132 0x6: decode CPNUM {
133 0xb: ExtensionRegLoadStore::extensionRegLoadStore();
134 }
135 0x7: decode OPCODE_24 {
136 0: decode OPCODE_4 {
137 0: decode CPNUM {
138 0xa, 0xb: decode OPCODE_23_20 {
139##include "vfp.isa"
140 }
141 } // CPNUM
142 1: decode CPNUM { // 27-24=1110,4 ==1
143 1: decode OPCODE_15_12 {
144 format FloatOp {
145 0xf: decode OPCODE_23_21 {
146 format FloatCmp {
147 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
148 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
149 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
150 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
151 }
152 }
153 default: decode OPCODE_23_20 {
154 0x0: decode OPCODE_7 {
155 0: flts({{ Fn.sf = (float) Rd.sw; }});
156 1: fltd({{ Fn.df = (double) Rd.sw; }});
157 }
158 0x1: decode OPCODE_7 {
159 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
160 1: fixd({{ Rd = (uint32_t) Fm.df; }});
161 }
162 0x2: wfs({{ Fpsr = Rd; }});
163 0x3: rfs({{ Rd = Fpsr; }});
164 0x4: FailUnimpl::wfc();
165 0x5: FailUnimpl::rfc();
166 }
167 } // format FloatOp
168 }
169 0xa: decode MISC_OPCODE {
170 0x1: decode MEDIA_OPCODE {
171 0xf: decode RN {
172 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
173 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
174 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
175 }
176 0xe: decode RN {
177 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
178 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
179 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
180 }
181 } // MEDIA_OPCODE (MISC_OPCODE 0x1)
182 } // MISC_OPCODE (CPNUM 0xA)
183 0xf: decode RN {
184 // Barrriers, Cache Maintence, NOPS
185 7: decode OPCODE_23_21 {
186 0: decode RM {
187 0: decode OPC2 {
188 4: decode OPCODE_20 {
189 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
190 }
191 }
192 1: WarnUnimpl::cp15_cache_maint();
193 4: WarnUnimpl::cp15_par();
194 5: decode OPC2 {
195 0,1: WarnUnimpl::cp15_cache_maint2();
196 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
197 6,7: WarnUnimpl::cp15_bp_maint();
198 }
199 6: WarnUnimpl::cp15_cache_maint3();
200 8: WarnUnimpl::cp15_va_to_pa();
201 10: decode OPC2 {
202 1,2: WarnUnimpl::cp15_cache_maint3();
203 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
204 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
205 }
206 11: WarnUnimpl::cp15_cache_maint4();
207 13: decode OPC2 {
208 1: decode OPCODE_20 {
209 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
210 }
211 }
212 14: WarnUnimpl::cp15_cache_maint5();
213 } // RM
214 } // OPCODE_23_21 CR
215
216 // Thread ID and context ID registers
217 // Thread ID register needs cheaper access than miscreg
218 13: WarnUnimpl::mcr_mrc_cp15_c7();
219
220 // All the rest
221 default: decode OPCODE_20 {
222 0: PredOp::mcr_cp15({{
223 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
224 }});
225 1: PredOp::mrc_cp15({{
226 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
227 }});
228 }
229 } // RN
230 } // CPNUM (OP4 == 1)
231 } //OPCODE_4
232
233 1: Svc::svc();
234 } // OPCODE_24
235
236}
237}
238}
239
|