1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
530: decode ENCODING {
54format DataOp {
55 0x0: decode SEVEN_AND_FOUR {
56 1: decode MISC_OPCODE {
57 0x9: decode PREPOST {
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
530: decode ENCODING {
54format DataOp {
55 0x0: decode SEVEN_AND_FOUR {
56 1: decode MISC_OPCODE {
57 0x9: decode PREPOST {
|
58 0: decode OPCODE {
59 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
60 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none);
61 0x2: WarnUnimpl::umall();
62 0x4: umull({{
63 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
64 Rd = (uint32_t)(resTemp & 0xffffffff);
65 Rn = (uint32_t)(resTemp >> 32);
66 }}, llbit);
67 0x5: smlal({{
68 resTemp = ((int64_t)Rm) * ((int64_t)Rs);
69 resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd);
70 Rd = (uint32_t)(resTemp & 0xffffffff);
71 Rn = (uint32_t)(resTemp >> 32);
72 }}, llbit);
73 0x6: smull({{
74 resTemp = ((int64_t)(int32_t)Rm)*
75 ((int64_t)(int32_t)Rs);
76 Rd = (int32_t)(resTemp & 0xffffffff);
77 Rn = (int32_t)(resTemp >> 32);
78 }}, llbit);
79 0x7: umlal({{
80 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
81 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
82 Rd = (uint32_t)(resTemp & 0xffffffff);
83 Rn = (uint32_t)(resTemp >> 32);
84 }}, llbit);
85 }
| 58 0: ArmMultAndMultAcc::armMultAndMultAcc();
|
86 1: decode PUBWL {
87 0x10: WarnUnimpl::swp();
88 0x14: WarnUnimpl::swpb();
89 0x18: WarnUnimpl::strex();
90 0x19: WarnUnimpl::ldrex();
91 }
92 }
93 0xb, 0xd, 0xf: AddrMode3::addrMode3();
94 }
95 0: decode IS_MISC {
96 0: ArmDataProcReg::armDataProcReg();
| 59 1: decode PUBWL {
60 0x10: WarnUnimpl::swp();
61 0x14: WarnUnimpl::swpb();
62 0x18: WarnUnimpl::strex();
63 0x19: WarnUnimpl::ldrex();
64 }
65 }
66 0xb, 0xd, 0xf: AddrMode3::addrMode3();
67 }
68 0: decode IS_MISC {
69 0: ArmDataProcReg::armDataProcReg();
|
97 1: decode MISC_OPCODE {
98 0x0: decode OPCODE {
99 0x8: PredOp::mrs_cpsr({{
100 Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
101 }});
102 0x9: decode USEIMM {
103 // The mask field is the same as the RN index.
104 0: PredOp::msr_cpsr_reg({{
105 uint32_t newCpsr =
106 cpsrWriteByInstr(Cpsr | CondCodes,
107 Rm, RN, false);
108 Cpsr = ~CondCodesMask & newCpsr;
109 CondCodes = CondCodesMask & newCpsr;
| 70 1: decode OPCODE_7 {
71 0x0: decode MISC_OPCODE {
72 0x0: decode OPCODE {
73 0x8: PredOp::mrs_cpsr({{
74 Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
|
110 }});
| 75 }});
|
111 1: PredImmOp::msr_cpsr_imm({{
112 uint32_t newCpsr =
113 cpsrWriteByInstr(Cpsr | CondCodes,
114 rotated_imm, RN, false);
115 Cpsr = ~CondCodesMask & newCpsr;
116 CondCodes = CondCodesMask & newCpsr;
117 }});
| 76 0x9: decode USEIMM {
77 // The mask field is the same as the RN index.
78 0: PredOp::msr_cpsr_reg({{
79 uint32_t newCpsr =
80 cpsrWriteByInstr(Cpsr | CondCodes,
81 Rm, RN, false);
82 Cpsr = ~CondCodesMask & newCpsr;
83 CondCodes = CondCodesMask & newCpsr;
84 }});
85 1: PredImmOp::msr_cpsr_imm({{
86 uint32_t newCpsr =
87 cpsrWriteByInstr(Cpsr | CondCodes,
88 rotated_imm, RN, false);
89 Cpsr = ~CondCodesMask & newCpsr;
90 CondCodes = CondCodesMask & newCpsr;
91 }});
92 }
93 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
94 0xb: decode USEIMM {
95 // The mask field is the same as the RN index.
96 0: PredOp::msr_spsr_reg({{
97 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
98 }});
99 1: PredImmOp::msr_spsr_imm({{
100 Spsr = spsrWriteByInstr(Spsr, rotated_imm,
101 RN, false);
102 }});
103 }
|
118 }
| 104 }
|
119 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
120 0xb: decode USEIMM {
121 // The mask field is the same as the RN index.
122 0: PredOp::msr_spsr_reg({{
123 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
| 105 0x1: decode OPCODE {
106 0x9: ArmBx::armBx();
107 0xb: PredOp::clz({{
108 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
|
124 }});
| 109 }});
|
125 1: PredImmOp::msr_spsr_imm({{
126 Spsr = spsrWriteByInstr(Spsr, rotated_imm,
127 RN, false);
128 }});
| |
129 }
| 110 }
|
| 111 0x2: decode OPCODE {
112 0x9: WarnUnimpl::bxj();
113 }
114 0x3: decode OPCODE {
115 0x9: ArmBlxReg::armBlxReg();
116 }
117 0x5: decode OPCODE {
118 0x8: WarnUnimpl::qadd();
119 0x9: WarnUnimpl::qsub();
120 0xa: WarnUnimpl::qdadd();
121 0xb: WarnUnimpl::qdsub();
122 }
|
130 }
| 123 }
|
131 0x1: decode OPCODE {
132 0x9: ArmBx::armBx();
133 0xb: PredOp::clz({{
134 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
135 }});
136 }
137 0x2: decode OPCODE {
138 0x9: WarnUnimpl::bxj();
139 }
140 0x3: decode OPCODE {
141 0x9: ArmBlxReg::armBlxReg();
142 }
143 0x5: decode OPCODE {
144 0x8: WarnUnimpl::qadd();
145 0x9: WarnUnimpl::qsub();
146 0xa: WarnUnimpl::qdadd();
147 0xb: WarnUnimpl::qdsub();
148 }
149 0x8: decode OPCODE {
150 0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
151 0x9: WarnUnimpl::smlalbb();
152 0xa: WarnUnimpl::smlawb();
153 0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none);
154 }
155 0xa: decode OPCODE {
156 0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
157 0x9: smulwb({{
158 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16);
159 }}, none);
160 0xa: WarnUnimpl::smlaltb();
161 0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none);
162 }
163 0xc: decode OPCODE {
164 0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
165 0x9: WarnUnimpl::smlawt();
166 0xa: WarnUnimpl::smlalbt();
167 0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none);
168 }
169 0xe: decode OPCODE {
170 0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
171 0x9: smulwt({{
172 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16);
173 }}, none);
174 0xa: WarnUnimpl::smlaltt();
175 0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none);
176 }
| 124 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
|
177 }
178 }
179 }
180 0x1: decode IS_MISC {
181 0: ArmDataProcImm::armDataProcImm();
182 1: decode OPCODE {
183 // The following two instructions aren't supposed to be defined
184 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
185 0x9: decode RN {
186 0: decode IMM {
187 0: PredImmOp::nop({{ ; }});
188 1: WarnUnimpl::yield();
189 2: WarnUnimpl::wfe();
190 3: WarnUnimpl::wfi();
191 4: WarnUnimpl::sev();
192 }
193 default: PredImmOp::msr_i_cpsr({{
194 uint32_t newCpsr =
195 cpsrWriteByInstr(Cpsr | CondCodes,
196 rotated_imm, RN, false);
197 Cpsr = ~CondCodesMask & newCpsr;
198 CondCodes = CondCodesMask & newCpsr;
199 }});
200 }
201 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
202 0xb: PredImmOp::msr_i_spsr({{
203 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
204 }});
205 }
206 }
207 0x2: AddrMode2::addrMode2(True);
208 0x3: decode OPCODE_4 {
209 0: AddrMode2::addrMode2(False);
| 125 }
126 }
127 }
128 0x1: decode IS_MISC {
129 0: ArmDataProcImm::armDataProcImm();
130 1: decode OPCODE {
131 // The following two instructions aren't supposed to be defined
132 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
133 0x9: decode RN {
134 0: decode IMM {
135 0: PredImmOp::nop({{ ; }});
136 1: WarnUnimpl::yield();
137 2: WarnUnimpl::wfe();
138 3: WarnUnimpl::wfi();
139 4: WarnUnimpl::sev();
140 }
141 default: PredImmOp::msr_i_cpsr({{
142 uint32_t newCpsr =
143 cpsrWriteByInstr(Cpsr | CondCodes,
144 rotated_imm, RN, false);
145 Cpsr = ~CondCodesMask & newCpsr;
146 CondCodes = CondCodesMask & newCpsr;
147 }});
148 }
149 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
150 0xb: PredImmOp::msr_i_spsr({{
151 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
152 }});
153 }
154 }
155 0x2: AddrMode2::addrMode2(True);
156 0x3: decode OPCODE_4 {
157 0: AddrMode2::addrMode2(False);
|
210 1: decode MEDIA_OPCODE {
211 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
212 0x8: decode MISC_OPCODE {
213 0x1, 0x9: WarnUnimpl::pkhbt();
214 0x7: WarnUnimpl::sxtab16();
215 0xb: WarnUnimpl::sel();
216 0x5, 0xd: WarnUnimpl::pkhtb();
217 0x3: WarnUnimpl::sign_zero_extend_add();
218 }
219 0xa, 0xb: decode SHIFT {
220 0x0, 0x2: WarnUnimpl::ssat();
221 0x1: WarnUnimpl::ssat16();
222 }
223 0xe, 0xf: decode SHIFT {
224 0x0, 0x2: WarnUnimpl::usat();
225 0x1: WarnUnimpl::usat16();
226 }
227 0x10: decode RN {
228 0xf: decode MISC_OPCODE {
229 0x1: WarnUnimpl::smuad();
230 0x3: WarnUnimpl::smuadx();
231 0x5: WarnUnimpl::smusd();
232 0x7: WarnUnimpl::smusdx();
| 158 1: decode OPCODE_24_23 {
159 0x0: WarnUnimpl::parallel_add_subtract_instructions();
160 0x1: decode MEDIA_OPCODE {
161 0x8: decode MISC_OPCODE {
162 0x1, 0x9: WarnUnimpl::pkhbt();
163 0x7: WarnUnimpl::sxtab16();
164 0xb: WarnUnimpl::sel();
165 0x5, 0xd: WarnUnimpl::pkhtb();
166 0x3: WarnUnimpl::sign_zero_extend_add();
|
233 }
| 167 }
|
234 default: decode MISC_OPCODE {
235 0x1: WarnUnimpl::smlad();
236 0x3: WarnUnimpl::smladx();
237 0x5: WarnUnimpl::smlsd();
238 0x7: WarnUnimpl::smlsdx();
| 168 0xa, 0xb: decode SHIFT {
169 0x0, 0x2: WarnUnimpl::ssat();
170 0x1: WarnUnimpl::ssat16();
|
239 }
| 171 }
|
| 172 0xe, 0xf: decode SHIFT {
173 0x0, 0x2: WarnUnimpl::usat();
174 0x1: WarnUnimpl::usat16();
175 }
|
240 }
| 176 }
|
241 0x14: decode MISC_OPCODE {
242 0x1: WarnUnimpl::smlald();
243 0x3: WarnUnimpl::smlaldx();
244 0x5: WarnUnimpl::smlsld();
245 0x7: WarnUnimpl::smlsldx();
246 }
247 0x15: decode RN {
248 0xf: decode MISC_OPCODE {
249 0x1: WarnUnimpl::smmul();
250 0x3: WarnUnimpl::smmulr();
| 177 0x2: ArmSignedMultiplies::armSignedMultiplies();
178 0x3: decode MEDIA_OPCODE {
179 0x18: decode RN {
180 0xf: WarnUnimpl::usada8();
181 default: WarnUnimpl::usad8();
|
251 }
| 182 }
|
252 default: decode MISC_OPCODE {
253 0x1: WarnUnimpl::smmla();
254 0x3: WarnUnimpl::smmlar();
255 0xd: WarnUnimpl::smmls();
256 0xf: WarnUnimpl::smmlsr();
257 }
| |
258 }
| 183 }
|
259 0x18: decode RN {
260 0xf: WarnUnimpl::usada8();
261 default: WarnUnimpl::usad8();
262 }
| |
263 }
264 }
265 0x4: ArmMacroMem::armMacroMem();
266 0x5: decode OPCODE_24 {
267 0: ArmBBlxImm::armBBlxImm();
268 1: ArmBlBlxImm::armBlBlxImm();
269 }
270 0x6: decode CPNUM {
271 0xb: decode LOADOP {
272 0x0: WarnUnimpl::fstmx();
273 0x1: WarnUnimpl::fldmx();
274 }
275 }
276 0x7: decode OPCODE_24 {
277 0: decode OPCODE_4 {
278 0: decode CPNUM {
279 0xa, 0xb: decode OPCODE_23_20 {
280##include "vfp.isa"
281 }
282 } // CPNUM
283 1: decode CPNUM { // 27-24=1110,4 ==1
284 1: decode OPCODE_15_12 {
285 format FloatOp {
286 0xf: decode OPCODE_23_21 {
287 format FloatCmp {
288 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
289 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
290 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
291 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
292 }
293 }
294 default: decode OPCODE_23_20 {
295 0x0: decode OPCODE_7 {
296 0: flts({{ Fn.sf = (float) Rd.sw; }});
297 1: fltd({{ Fn.df = (double) Rd.sw; }});
298 }
299 0x1: decode OPCODE_7 {
300 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
301 1: fixd({{ Rd = (uint32_t) Fm.df; }});
302 }
303 0x2: wfs({{ Fpsr = Rd; }});
304 0x3: rfs({{ Rd = Fpsr; }});
305 0x4: FailUnimpl::wfc();
306 0x5: FailUnimpl::rfc();
307 }
308 } // format FloatOp
309 }
310 0xa: decode MISC_OPCODE {
311 0x1: decode MEDIA_OPCODE {
312 0xf: decode RN {
313 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
314 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
315 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
316 }
317 0xe: decode RN {
318 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
319 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
320 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
321 }
322 } // MEDIA_OPCODE (MISC_OPCODE 0x1)
323 } // MISC_OPCODE (CPNUM 0xA)
324 0xf: decode RN {
325 // Barrriers, Cache Maintence, NOPS
326 7: decode OPCODE_23_21 {
327 0: decode RM {
328 0: decode OPC2 {
329 4: decode OPCODE_20 {
330 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
331 }
332 }
333 1: WarnUnimpl::cp15_cache_maint();
334 4: WarnUnimpl::cp15_par();
335 5: decode OPC2 {
336 0,1: WarnUnimpl::cp15_cache_maint2();
337 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
338 6,7: WarnUnimpl::cp15_bp_maint();
339 }
340 6: WarnUnimpl::cp15_cache_maint3();
341 8: WarnUnimpl::cp15_va_to_pa();
342 10: decode OPC2 {
343 1,2: WarnUnimpl::cp15_cache_maint3();
344 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
345 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
346 }
347 11: WarnUnimpl::cp15_cache_maint4();
348 13: decode OPC2 {
349 1: decode OPCODE_20 {
350 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
351 }
352 }
353 14: WarnUnimpl::cp15_cache_maint5();
354 } // RM
355 } // OPCODE_23_21 CR
356
357 // Thread ID and context ID registers
358 // Thread ID register needs cheaper access than miscreg
359 13: WarnUnimpl::mcr_mrc_cp15_c7();
360
361 // All the rest
362 default: decode OPCODE_20 {
363 0: PredOp::mcr_cp15({{
364 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
365 }});
366 1: PredOp::mrc_cp15({{
367 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
368 }});
369 }
370 } // RN
371 } // CPNUM (OP4 == 1)
372 } //OPCODE_4
373
374#if FULL_SYSTEM
375 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
376#else
377 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode))
378 {
379 if (IMMED_23_0)
380 xc->syscall(IMMED_23_0);
381 else
382 xc->syscall(R7);
383 }
384 }});
385#endif // FULL_SYSTEM
386 } // OPCODE_24
387
388}
389}
390
| 184 }
185 }
186 0x4: ArmMacroMem::armMacroMem();
187 0x5: decode OPCODE_24 {
188 0: ArmBBlxImm::armBBlxImm();
189 1: ArmBlBlxImm::armBlBlxImm();
190 }
191 0x6: decode CPNUM {
192 0xb: decode LOADOP {
193 0x0: WarnUnimpl::fstmx();
194 0x1: WarnUnimpl::fldmx();
195 }
196 }
197 0x7: decode OPCODE_24 {
198 0: decode OPCODE_4 {
199 0: decode CPNUM {
200 0xa, 0xb: decode OPCODE_23_20 {
201##include "vfp.isa"
202 }
203 } // CPNUM
204 1: decode CPNUM { // 27-24=1110,4 ==1
205 1: decode OPCODE_15_12 {
206 format FloatOp {
207 0xf: decode OPCODE_23_21 {
208 format FloatCmp {
209 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
210 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
211 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
212 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
213 }
214 }
215 default: decode OPCODE_23_20 {
216 0x0: decode OPCODE_7 {
217 0: flts({{ Fn.sf = (float) Rd.sw; }});
218 1: fltd({{ Fn.df = (double) Rd.sw; }});
219 }
220 0x1: decode OPCODE_7 {
221 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
222 1: fixd({{ Rd = (uint32_t) Fm.df; }});
223 }
224 0x2: wfs({{ Fpsr = Rd; }});
225 0x3: rfs({{ Rd = Fpsr; }});
226 0x4: FailUnimpl::wfc();
227 0x5: FailUnimpl::rfc();
228 }
229 } // format FloatOp
230 }
231 0xa: decode MISC_OPCODE {
232 0x1: decode MEDIA_OPCODE {
233 0xf: decode RN {
234 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
235 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
236 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
237 }
238 0xe: decode RN {
239 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
240 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
241 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
242 }
243 } // MEDIA_OPCODE (MISC_OPCODE 0x1)
244 } // MISC_OPCODE (CPNUM 0xA)
245 0xf: decode RN {
246 // Barrriers, Cache Maintence, NOPS
247 7: decode OPCODE_23_21 {
248 0: decode RM {
249 0: decode OPC2 {
250 4: decode OPCODE_20 {
251 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
252 }
253 }
254 1: WarnUnimpl::cp15_cache_maint();
255 4: WarnUnimpl::cp15_par();
256 5: decode OPC2 {
257 0,1: WarnUnimpl::cp15_cache_maint2();
258 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
259 6,7: WarnUnimpl::cp15_bp_maint();
260 }
261 6: WarnUnimpl::cp15_cache_maint3();
262 8: WarnUnimpl::cp15_va_to_pa();
263 10: decode OPC2 {
264 1,2: WarnUnimpl::cp15_cache_maint3();
265 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
266 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
267 }
268 11: WarnUnimpl::cp15_cache_maint4();
269 13: decode OPC2 {
270 1: decode OPCODE_20 {
271 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
272 }
273 }
274 14: WarnUnimpl::cp15_cache_maint5();
275 } // RM
276 } // OPCODE_23_21 CR
277
278 // Thread ID and context ID registers
279 // Thread ID register needs cheaper access than miscreg
280 13: WarnUnimpl::mcr_mrc_cp15_c7();
281
282 // All the rest
283 default: decode OPCODE_20 {
284 0: PredOp::mcr_cp15({{
285 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
286 }});
287 1: PredOp::mrc_cp15({{
288 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
289 }});
290 }
291 } // RN
292 } // CPNUM (OP4 == 1)
293 } //OPCODE_4
294
295#if FULL_SYSTEM
296 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
297#else
298 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode))
299 {
300 if (IMMED_23_0)
301 xc->syscall(IMMED_23_0);
302 else
303 xc->syscall(R7);
304 }
305 }});
306#endif // FULL_SYSTEM
307 } // OPCODE_24
308
309}
310}
311
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