1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
530: decode ENCODING {
54format DataOp {
55 0x0: decode SEVEN_AND_FOUR {
56 1: decode MISC_OPCODE {
57 0x9: decode PREPOST {
58 0: decode OPCODE {
59 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
60 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none);
61 0x2: WarnUnimpl::umall();
62 0x4: umull({{
63 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
64 Rd = (uint32_t)(resTemp & 0xffffffff);
65 Rn = (uint32_t)(resTemp >> 32);
66 }}, llbit);
67 0x5: smlal({{
68 resTemp = ((int64_t)Rm) * ((int64_t)Rs);
69 resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd);
70 Rd = (uint32_t)(resTemp & 0xffffffff);
71 Rn = (uint32_t)(resTemp >> 32);
72 }}, llbit);
73 0x6: smull({{
74 resTemp = ((int64_t)(int32_t)Rm)*
75 ((int64_t)(int32_t)Rs);
76 Rd = (int32_t)(resTemp & 0xffffffff);
77 Rn = (int32_t)(resTemp >> 32);
78 }}, llbit);
79 0x7: umlal({{
80 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
81 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
82 Rd = (uint32_t)(resTemp & 0xffffffff);
83 Rn = (uint32_t)(resTemp >> 32);
84 }}, llbit);
85 }
86 1: decode PUBWL {
87 0x10: WarnUnimpl::swp();
88 0x14: WarnUnimpl::swpb();
89 0x18: WarnUnimpl::strex();
90 0x19: WarnUnimpl::ldrex();
91 }
92 }
93 0xb, 0xd, 0xf: AddrMode3::addrMode3();
94 }
95 0: decode IS_MISC {
96 0: decode OPCODE {
97 0x0: and({{ Rd = resTemp = Rn & op2; }});
98 0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
99 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
100 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
101 0x4: add({{ Rd = resTemp = Rn + op2; }}, add);
102 0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add);
103 0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub);
104 0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb);
105 0x8: tst({{ resTemp = Rn & op2; }});
106 0x9: teq({{ resTemp = Rn ^ op2; }});
107 0xa: cmp({{ resTemp = Rn - op2; }}, sub);
108 0xb: cmn({{ resTemp = Rn + op2; }}, add);
109 0xc: orr({{ Rd = resTemp = Rn | op2; }});
110 0xd: mov({{ Rd = resTemp = op2; }});
111 0xe: bic({{ Rd = resTemp = Rn & ~op2; }});
112 0xf: mvn({{ Rd = resTemp = ~op2; }});
113 }
114 1: decode MISC_OPCODE {
115 0x0: decode OPCODE {
116 0x8: PredOp::mrs_cpsr({{
117 Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
118 }});
119 0x9: decode USEIMM {
120 // The mask field is the same as the RN index.
121 0: PredOp::msr_cpsr_reg({{
122 uint32_t newCpsr =
123 cpsrWriteByInstr(Cpsr | CondCodes,
124 Rm, RN, false);
125 Cpsr = ~CondCodesMask & newCpsr;
126 CondCodes = CondCodesMask & newCpsr;
127 }});
128 1: PredImmOp::msr_cpsr_imm({{
129 uint32_t newCpsr =
130 cpsrWriteByInstr(Cpsr | CondCodes,
131 rotated_imm, RN, false);
132 Cpsr = ~CondCodesMask & newCpsr;
133 CondCodes = CondCodesMask & newCpsr;
134 }});
135 }
136 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
137 0xb: decode USEIMM {
138 // The mask field is the same as the RN index.
139 0: PredOp::msr_spsr_reg({{
140 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
141 }});
142 1: PredImmOp::msr_spsr_imm({{
143 Spsr = spsrWriteByInstr(Spsr, rotated_imm,
144 RN, false);
145 }});
146 }
147 }
148 0x1: decode OPCODE {
149 0x9: BranchExchange::bx({{ }});
150 0xb: PredOp::clz({{
151 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
152 }});
153 }
154 0x2: decode OPCODE {
155 0x9: WarnUnimpl::bxj();
156 }
157 0x3: decode OPCODE {
158 0x9: BranchExchange::blx({{ }}, Link);
159 }
160 0x5: decode OPCODE {
161 0x8: WarnUnimpl::qadd();
162 0x9: WarnUnimpl::qsub();
163 0xa: WarnUnimpl::qdadd();
164 0xb: WarnUnimpl::qdsub();
165 }
166 0x8: decode OPCODE {
167 0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
168 0x9: WarnUnimpl::smlalbb();
169 0xa: WarnUnimpl::smlawb();
170 0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none);
171 }
172 0xa: decode OPCODE {
173 0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
174 0x9: smulwb({{
175 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16);
176 }}, none);
177 0xa: WarnUnimpl::smlaltb();
178 0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none);
179 }
180 0xc: decode OPCODE {
181 0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
182 0x9: WarnUnimpl::smlawt();
183 0xa: WarnUnimpl::smlalbt();
184 0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none);
185 }
186 0xe: decode OPCODE {
187 0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
188 0x9: smulwt({{
189 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16);
190 }}, none);
191 0xa: WarnUnimpl::smlaltt();
192 0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none);
193 }
194 }
195 }
196 }
197 0x1: decode IS_MISC {
198 0: decode OPCODE {
199 format DataImmOp {
200 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }});
201 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }});
202 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub);
203 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb);
204 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add);
205 0x5: adci({{
206 Rd = resTemp = Rn + rotated_imm + CondCodes<29:>;
207 }}, add);
208 0x6: sbci({{
209 Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>;
210 }}, sub);
211 0x7: rsci({{
212 Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>;
213 }}, rsb);
214 0x8: tsti({{ resTemp = Rn & rotated_imm; }});
215 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }});
216 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub);
217 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add);
218 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }});
219 0xd: movi({{ Rd = resTemp = rotated_imm; }});
220 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }});
221 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }});
222 }
223 }
224 1: decode OPCODE {
225 // The following two instructions aren't supposed to be defined
226 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
227 0x9: decode RN {
228 0: decode IMM {
229 0: PredImmOp::nop({{ ; }});
230 1: WarnUnimpl::yield();
231 2: WarnUnimpl::wfe();
232 3: WarnUnimpl::wfi();
233 4: WarnUnimpl::sev();
234 }
235 default: PredImmOp::msr_i_cpsr({{
236 uint32_t newCpsr =
237 cpsrWriteByInstr(Cpsr | CondCodes,
238 rotated_imm, RN, false);
239 Cpsr = ~CondCodesMask & newCpsr;
240 CondCodes = CondCodesMask & newCpsr;
241 }});
242 }
243 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
244 0xb: PredImmOp::msr_i_spsr({{
245 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
246 }});
247 }
248 }
249 0x2: AddrMode2::addrMode2(True);
250 0x3: decode OPCODE_4 {
251 0: AddrMode2::addrMode2(False);
252 1: decode MEDIA_OPCODE {
253 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
254 0x8: decode MISC_OPCODE {
255 0x1, 0x9: WarnUnimpl::pkhbt();
256 0x7: WarnUnimpl::sxtab16();
257 0xb: WarnUnimpl::sel();
258 0x5, 0xd: WarnUnimpl::pkhtb();
259 0x3: WarnUnimpl::sign_zero_extend_add();
260 }
261 0xa, 0xb: decode SHIFT {
262 0x0, 0x2: WarnUnimpl::ssat();
263 0x1: WarnUnimpl::ssat16();
264 }
265 0xe, 0xf: decode SHIFT {
266 0x0, 0x2: WarnUnimpl::usat();
267 0x1: WarnUnimpl::usat16();
268 }
269 0x10: decode RN {
270 0xf: decode MISC_OPCODE {
271 0x1: WarnUnimpl::smuad();
272 0x3: WarnUnimpl::smuadx();
273 0x5: WarnUnimpl::smusd();
274 0x7: WarnUnimpl::smusdx();
275 }
276 default: decode MISC_OPCODE {
277 0x1: WarnUnimpl::smlad();
278 0x3: WarnUnimpl::smladx();
279 0x5: WarnUnimpl::smlsd();
280 0x7: WarnUnimpl::smlsdx();
281 }
282 }
283 0x14: decode MISC_OPCODE {
284 0x1: WarnUnimpl::smlald();
285 0x3: WarnUnimpl::smlaldx();
286 0x5: WarnUnimpl::smlsld();
287 0x7: WarnUnimpl::smlsldx();
288 }
289 0x15: decode RN {
290 0xf: decode MISC_OPCODE {
291 0x1: WarnUnimpl::smmul();
292 0x3: WarnUnimpl::smmulr();
293 }
294 default: decode MISC_OPCODE {
295 0x1: WarnUnimpl::smmla();
296 0x3: WarnUnimpl::smmlar();
297 0xd: WarnUnimpl::smmls();
298 0xf: WarnUnimpl::smmlsr();
299 }
300 }
301 0x18: decode RN {
302 0xf: WarnUnimpl::usada8();
303 default: WarnUnimpl::usad8();
304 }
305 }
306 }
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
530: decode ENCODING {
54format DataOp {
55 0x0: decode SEVEN_AND_FOUR {
56 1: decode MISC_OPCODE {
57 0x9: decode PREPOST {
58 0: decode OPCODE {
59 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
60 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none);
61 0x2: WarnUnimpl::umall();
62 0x4: umull({{
63 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
64 Rd = (uint32_t)(resTemp & 0xffffffff);
65 Rn = (uint32_t)(resTemp >> 32);
66 }}, llbit);
67 0x5: smlal({{
68 resTemp = ((int64_t)Rm) * ((int64_t)Rs);
69 resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd);
70 Rd = (uint32_t)(resTemp & 0xffffffff);
71 Rn = (uint32_t)(resTemp >> 32);
72 }}, llbit);
73 0x6: smull({{
74 resTemp = ((int64_t)(int32_t)Rm)*
75 ((int64_t)(int32_t)Rs);
76 Rd = (int32_t)(resTemp & 0xffffffff);
77 Rn = (int32_t)(resTemp >> 32);
78 }}, llbit);
79 0x7: umlal({{
80 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
81 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
82 Rd = (uint32_t)(resTemp & 0xffffffff);
83 Rn = (uint32_t)(resTemp >> 32);
84 }}, llbit);
85 }
86 1: decode PUBWL {
87 0x10: WarnUnimpl::swp();
88 0x14: WarnUnimpl::swpb();
89 0x18: WarnUnimpl::strex();
90 0x19: WarnUnimpl::ldrex();
91 }
92 }
93 0xb, 0xd, 0xf: AddrMode3::addrMode3();
94 }
95 0: decode IS_MISC {
96 0: decode OPCODE {
97 0x0: and({{ Rd = resTemp = Rn & op2; }});
98 0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
99 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
100 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
101 0x4: add({{ Rd = resTemp = Rn + op2; }}, add);
102 0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add);
103 0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub);
104 0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb);
105 0x8: tst({{ resTemp = Rn & op2; }});
106 0x9: teq({{ resTemp = Rn ^ op2; }});
107 0xa: cmp({{ resTemp = Rn - op2; }}, sub);
108 0xb: cmn({{ resTemp = Rn + op2; }}, add);
109 0xc: orr({{ Rd = resTemp = Rn | op2; }});
110 0xd: mov({{ Rd = resTemp = op2; }});
111 0xe: bic({{ Rd = resTemp = Rn & ~op2; }});
112 0xf: mvn({{ Rd = resTemp = ~op2; }});
113 }
114 1: decode MISC_OPCODE {
115 0x0: decode OPCODE {
116 0x8: PredOp::mrs_cpsr({{
117 Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
118 }});
119 0x9: decode USEIMM {
120 // The mask field is the same as the RN index.
121 0: PredOp::msr_cpsr_reg({{
122 uint32_t newCpsr =
123 cpsrWriteByInstr(Cpsr | CondCodes,
124 Rm, RN, false);
125 Cpsr = ~CondCodesMask & newCpsr;
126 CondCodes = CondCodesMask & newCpsr;
127 }});
128 1: PredImmOp::msr_cpsr_imm({{
129 uint32_t newCpsr =
130 cpsrWriteByInstr(Cpsr | CondCodes,
131 rotated_imm, RN, false);
132 Cpsr = ~CondCodesMask & newCpsr;
133 CondCodes = CondCodesMask & newCpsr;
134 }});
135 }
136 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
137 0xb: decode USEIMM {
138 // The mask field is the same as the RN index.
139 0: PredOp::msr_spsr_reg({{
140 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
141 }});
142 1: PredImmOp::msr_spsr_imm({{
143 Spsr = spsrWriteByInstr(Spsr, rotated_imm,
144 RN, false);
145 }});
146 }
147 }
148 0x1: decode OPCODE {
149 0x9: BranchExchange::bx({{ }});
150 0xb: PredOp::clz({{
151 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
152 }});
153 }
154 0x2: decode OPCODE {
155 0x9: WarnUnimpl::bxj();
156 }
157 0x3: decode OPCODE {
158 0x9: BranchExchange::blx({{ }}, Link);
159 }
160 0x5: decode OPCODE {
161 0x8: WarnUnimpl::qadd();
162 0x9: WarnUnimpl::qsub();
163 0xa: WarnUnimpl::qdadd();
164 0xb: WarnUnimpl::qdsub();
165 }
166 0x8: decode OPCODE {
167 0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
168 0x9: WarnUnimpl::smlalbb();
169 0xa: WarnUnimpl::smlawb();
170 0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none);
171 }
172 0xa: decode OPCODE {
173 0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
174 0x9: smulwb({{
175 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16);
176 }}, none);
177 0xa: WarnUnimpl::smlaltb();
178 0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none);
179 }
180 0xc: decode OPCODE {
181 0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
182 0x9: WarnUnimpl::smlawt();
183 0xa: WarnUnimpl::smlalbt();
184 0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none);
185 }
186 0xe: decode OPCODE {
187 0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
188 0x9: smulwt({{
189 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16);
190 }}, none);
191 0xa: WarnUnimpl::smlaltt();
192 0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none);
193 }
194 }
195 }
196 }
197 0x1: decode IS_MISC {
198 0: decode OPCODE {
199 format DataImmOp {
200 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }});
201 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }});
202 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub);
203 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb);
204 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add);
205 0x5: adci({{
206 Rd = resTemp = Rn + rotated_imm + CondCodes<29:>;
207 }}, add);
208 0x6: sbci({{
209 Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>;
210 }}, sub);
211 0x7: rsci({{
212 Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>;
213 }}, rsb);
214 0x8: tsti({{ resTemp = Rn & rotated_imm; }});
215 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }});
216 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub);
217 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add);
218 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }});
219 0xd: movi({{ Rd = resTemp = rotated_imm; }});
220 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }});
221 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }});
222 }
223 }
224 1: decode OPCODE {
225 // The following two instructions aren't supposed to be defined
226 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
227 0x9: decode RN {
228 0: decode IMM {
229 0: PredImmOp::nop({{ ; }});
230 1: WarnUnimpl::yield();
231 2: WarnUnimpl::wfe();
232 3: WarnUnimpl::wfi();
233 4: WarnUnimpl::sev();
234 }
235 default: PredImmOp::msr_i_cpsr({{
236 uint32_t newCpsr =
237 cpsrWriteByInstr(Cpsr | CondCodes,
238 rotated_imm, RN, false);
239 Cpsr = ~CondCodesMask & newCpsr;
240 CondCodes = CondCodesMask & newCpsr;
241 }});
242 }
243 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
244 0xb: PredImmOp::msr_i_spsr({{
245 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
246 }});
247 }
248 }
249 0x2: AddrMode2::addrMode2(True);
250 0x3: decode OPCODE_4 {
251 0: AddrMode2::addrMode2(False);
252 1: decode MEDIA_OPCODE {
253 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
254 0x8: decode MISC_OPCODE {
255 0x1, 0x9: WarnUnimpl::pkhbt();
256 0x7: WarnUnimpl::sxtab16();
257 0xb: WarnUnimpl::sel();
258 0x5, 0xd: WarnUnimpl::pkhtb();
259 0x3: WarnUnimpl::sign_zero_extend_add();
260 }
261 0xa, 0xb: decode SHIFT {
262 0x0, 0x2: WarnUnimpl::ssat();
263 0x1: WarnUnimpl::ssat16();
264 }
265 0xe, 0xf: decode SHIFT {
266 0x0, 0x2: WarnUnimpl::usat();
267 0x1: WarnUnimpl::usat16();
268 }
269 0x10: decode RN {
270 0xf: decode MISC_OPCODE {
271 0x1: WarnUnimpl::smuad();
272 0x3: WarnUnimpl::smuadx();
273 0x5: WarnUnimpl::smusd();
274 0x7: WarnUnimpl::smusdx();
275 }
276 default: decode MISC_OPCODE {
277 0x1: WarnUnimpl::smlad();
278 0x3: WarnUnimpl::smladx();
279 0x5: WarnUnimpl::smlsd();
280 0x7: WarnUnimpl::smlsdx();
281 }
282 }
283 0x14: decode MISC_OPCODE {
284 0x1: WarnUnimpl::smlald();
285 0x3: WarnUnimpl::smlaldx();
286 0x5: WarnUnimpl::smlsld();
287 0x7: WarnUnimpl::smlsldx();
288 }
289 0x15: decode RN {
290 0xf: decode MISC_OPCODE {
291 0x1: WarnUnimpl::smmul();
292 0x3: WarnUnimpl::smmulr();
293 }
294 default: decode MISC_OPCODE {
295 0x1: WarnUnimpl::smmla();
296 0x3: WarnUnimpl::smmlar();
297 0xd: WarnUnimpl::smmls();
298 0xf: WarnUnimpl::smmlsr();
299 }
300 }
301 0x18: decode RN {
302 0xf: WarnUnimpl::usada8();
303 default: WarnUnimpl::usad8();
304 }
305 }
306 }
|
311 0x5: decode OPCODE_24 {
312 // Branch (and Link) Instructions
313 0: Branch::b({{ }});
314 1: Branch::bl({{ }}, Link);
315 }
316 0x6: decode CPNUM {
317 0xb: decode LOADOP {
318 0x0: WarnUnimpl::fstmx();
319 0x1: WarnUnimpl::fldmx();
320 }
321 }
322 0x7: decode OPCODE_24 {
323 0: decode OPCODE_4 {
324 0: decode CPNUM {
325 0xa, 0xb: decode OPCODE_23_20 {
326##include "vfp.isa"
327 }
328 } // CPNUM
329 1: decode CPNUM { // 27-24=1110,4 ==1
330 1: decode OPCODE_15_12 {
331 format FloatOp {
332 0xf: decode OPCODE_23_21 {
333 format FloatCmp {
334 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
335 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
336 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
337 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
338 }
339 }
340 default: decode OPCODE_23_20 {
341 0x0: decode OPCODE_7 {
342 0: flts({{ Fn.sf = (float) Rd.sw; }});
343 1: fltd({{ Fn.df = (double) Rd.sw; }});
344 }
345 0x1: decode OPCODE_7 {
346 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
347 1: fixd({{ Rd = (uint32_t) Fm.df; }});
348 }
349 0x2: wfs({{ Fpsr = Rd; }});
350 0x3: rfs({{ Rd = Fpsr; }});
351 0x4: FailUnimpl::wfc();
352 0x5: FailUnimpl::rfc();
353 }
354 } // format FloatOp
355 }
356 0xa: decode MISC_OPCODE {
357 0x1: decode MEDIA_OPCODE {
358 0xf: decode RN {
359 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
360 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
361 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
362 }
363 0xe: decode RN {
364 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
365 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
366 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
367 }
368 } // MEDIA_OPCODE (MISC_OPCODE 0x1)
369 } // MISC_OPCODE (CPNUM 0xA)
370 0xf: decode RN {
371 // Barrriers, Cache Maintence, NOPS
372 7: decode OPCODE_23_21 {
373 0: decode RM {
374 0: decode OPC2 {
375 4: decode OPCODE_20 {
376 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
377 }
378 }
379 1: WarnUnimpl::cp15_cache_maint();
380 4: WarnUnimpl::cp15_par();
381 5: decode OPC2 {
382 0,1: WarnUnimpl::cp15_cache_maint2();
383 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
384 6,7: WarnUnimpl::cp15_bp_maint();
385 }
386 6: WarnUnimpl::cp15_cache_maint3();
387 8: WarnUnimpl::cp15_va_to_pa();
388 10: decode OPC2 {
389 1,2: WarnUnimpl::cp15_cache_maint3();
390 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
391 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
392 }
393 11: WarnUnimpl::cp15_cache_maint4();
394 13: decode OPC2 {
395 1: decode OPCODE_20 {
396 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
397 }
398 }
399 14: WarnUnimpl::cp15_cache_maint5();
400 } // RM
401 } // OPCODE_23_21 CR
402
403 // Thread ID and context ID registers
404 // Thread ID register needs cheaper access than miscreg
405 13: WarnUnimpl::mcr_mrc_cp15_c7();
406
407 // All the rest
408 default: decode OPCODE_20 {
409 0: PredOp::mcr_cp15({{
410 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
411 }});
412 1: PredOp::mrc_cp15({{
413 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
414 }});
415 }
416 } // RN
417 } // CPNUM (OP4 == 1)
418 } //OPCODE_4
419
420#if FULL_SYSTEM
421 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
422#else
423 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode))
424 {
425 if (IMMED_23_0)
426 xc->syscall(IMMED_23_0);
427 else
428 xc->syscall(R7);
429 }
430 }});
431#endif // FULL_SYSTEM
432 } // OPCODE_24
433
434}
435}
436
| 308 0x5: decode OPCODE_24 {
309 // Branch (and Link) Instructions
310 0: Branch::b({{ }});
311 1: Branch::bl({{ }}, Link);
312 }
313 0x6: decode CPNUM {
314 0xb: decode LOADOP {
315 0x0: WarnUnimpl::fstmx();
316 0x1: WarnUnimpl::fldmx();
317 }
318 }
319 0x7: decode OPCODE_24 {
320 0: decode OPCODE_4 {
321 0: decode CPNUM {
322 0xa, 0xb: decode OPCODE_23_20 {
323##include "vfp.isa"
324 }
325 } // CPNUM
326 1: decode CPNUM { // 27-24=1110,4 ==1
327 1: decode OPCODE_15_12 {
328 format FloatOp {
329 0xf: decode OPCODE_23_21 {
330 format FloatCmp {
331 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
332 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
333 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
334 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
335 }
336 }
337 default: decode OPCODE_23_20 {
338 0x0: decode OPCODE_7 {
339 0: flts({{ Fn.sf = (float) Rd.sw; }});
340 1: fltd({{ Fn.df = (double) Rd.sw; }});
341 }
342 0x1: decode OPCODE_7 {
343 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
344 1: fixd({{ Rd = (uint32_t) Fm.df; }});
345 }
346 0x2: wfs({{ Fpsr = Rd; }});
347 0x3: rfs({{ Rd = Fpsr; }});
348 0x4: FailUnimpl::wfc();
349 0x5: FailUnimpl::rfc();
350 }
351 } // format FloatOp
352 }
353 0xa: decode MISC_OPCODE {
354 0x1: decode MEDIA_OPCODE {
355 0xf: decode RN {
356 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
357 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
358 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
359 }
360 0xe: decode RN {
361 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
362 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
363 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
364 }
365 } // MEDIA_OPCODE (MISC_OPCODE 0x1)
366 } // MISC_OPCODE (CPNUM 0xA)
367 0xf: decode RN {
368 // Barrriers, Cache Maintence, NOPS
369 7: decode OPCODE_23_21 {
370 0: decode RM {
371 0: decode OPC2 {
372 4: decode OPCODE_20 {
373 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
374 }
375 }
376 1: WarnUnimpl::cp15_cache_maint();
377 4: WarnUnimpl::cp15_par();
378 5: decode OPC2 {
379 0,1: WarnUnimpl::cp15_cache_maint2();
380 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
381 6,7: WarnUnimpl::cp15_bp_maint();
382 }
383 6: WarnUnimpl::cp15_cache_maint3();
384 8: WarnUnimpl::cp15_va_to_pa();
385 10: decode OPC2 {
386 1,2: WarnUnimpl::cp15_cache_maint3();
387 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
388 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
389 }
390 11: WarnUnimpl::cp15_cache_maint4();
391 13: decode OPC2 {
392 1: decode OPCODE_20 {
393 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
394 }
395 }
396 14: WarnUnimpl::cp15_cache_maint5();
397 } // RM
398 } // OPCODE_23_21 CR
399
400 // Thread ID and context ID registers
401 // Thread ID register needs cheaper access than miscreg
402 13: WarnUnimpl::mcr_mrc_cp15_c7();
403
404 // All the rest
405 default: decode OPCODE_20 {
406 0: PredOp::mcr_cp15({{
407 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
408 }});
409 1: PredOp::mrc_cp15({{
410 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
411 }});
412 }
413 } // RN
414 } // CPNUM (OP4 == 1)
415 } //OPCODE_4
416
417#if FULL_SYSTEM
418 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
419#else
420 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode))
421 {
422 if (IMMED_23_0)
423 xc->syscall(IMMED_23_0);
424 else
425 xc->syscall(R7);
426 }
427 }});
428#endif // FULL_SYSTEM
429 } // OPCODE_24
430
431}
432}
433
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