1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
530: decode ENCODING {
54format DataOp {
55 0x0: decode SEVEN_AND_FOUR {
56 1: decode MISC_OPCODE {
57 0x9: decode PREPOST {
58 0: decode OPCODE {
59 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
60 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none);
61 0x2: WarnUnimpl::umall();
62 0x4: umull({{
63 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
64 Rd = (uint32_t)(resTemp & 0xffffffff);
65 Rn = (uint32_t)(resTemp >> 32);
66 }}, llbit);
67 0x5: smlal({{
68 resTemp = ((int64_t)Rm) * ((int64_t)Rs);
69 resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd);
70 Rd = (uint32_t)(resTemp & 0xffffffff);
71 Rn = (uint32_t)(resTemp >> 32);
72 }}, llbit);
73 0x6: smull({{
74 resTemp = ((int64_t)(int32_t)Rm)*
75 ((int64_t)(int32_t)Rs);
76 Rd = (int32_t)(resTemp & 0xffffffff);
77 Rn = (int32_t)(resTemp >> 32);
78 }}, llbit);
79 0x7: umlal({{
80 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
81 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
82 Rd = (uint32_t)(resTemp & 0xffffffff);
83 Rn = (uint32_t)(resTemp >> 32);
84 }}, llbit);
85 }
86 1: decode PUBWL {
87 0x10: WarnUnimpl::swp();
88 0x14: WarnUnimpl::swpb();
89 0x18: WarnUnimpl::strex();
90 0x19: WarnUnimpl::ldrex();
91 }
92 }
93 format AddrMode3 {
94 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }},
95 load, {{ Rd = Mem.uh; }});
96 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0);
97 Rdo = bits(Mem.ud, 63, 32); }},
98 load, {{ Rd = Mem.sb; }});
99 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) |
100 (Rdo.ud << 32); }},
101 load, {{ Rd = Mem.sh; }});
102 }
103 }
104 0: decode IS_MISC {
105 0: decode OPCODE {
106 0x0: and({{ Rd = resTemp = Rn & op2; }});
107 0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
108 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
109 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
110 0x4: add({{ Rd = resTemp = Rn + op2; }}, add);
111 0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add);
112 0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub);
113 0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb);
114 0x8: tst({{ resTemp = Rn & op2; }});
115 0x9: teq({{ resTemp = Rn ^ op2; }});
116 0xa: cmp({{ resTemp = Rn - op2; }}, sub);
117 0xb: cmn({{ resTemp = Rn + op2; }}, add);
118 0xc: orr({{ Rd = resTemp = Rn | op2; }});
119 0xd: mov({{ Rd = resTemp = op2; }});
120 0xe: bic({{ Rd = resTemp = Rn & ~op2; }});
121 0xf: mvn({{ Rd = resTemp = ~op2; }});
122 }
123 1: decode MISC_OPCODE {
124 0x0: decode OPCODE {
125 0x8: PredOp::mrs_cpsr({{
126 Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
127 }});
128 0x9: decode USEIMM {
129 // The mask field is the same as the RN index.
130 0: PredOp::msr_cpsr_reg({{
131 uint32_t newCpsr =
132 cpsrWriteByInstr(Cpsr | CondCodes,
133 Rm, RN, false);
134 Cpsr = ~CondCodesMask & newCpsr;
135 CondCodes = CondCodesMask & newCpsr;
136 }});
137 1: PredImmOp::msr_cpsr_imm({{
138 uint32_t newCpsr =
139 cpsrWriteByInstr(Cpsr | CondCodes,
140 rotated_imm, RN, false);
141 Cpsr = ~CondCodesMask & newCpsr;
142 CondCodes = CondCodesMask & newCpsr;
143 }});
144 }
145 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
146 0xb: decode USEIMM {
147 // The mask field is the same as the RN index.
148 0: PredOp::msr_spsr_reg({{
149 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
150 }});
151 1: PredImmOp::msr_spsr_imm({{
152 Spsr = spsrWriteByInstr(Spsr, rotated_imm,
153 RN, false);
154 }});
155 }
156 }
157 0x1: decode OPCODE {
158 0x9: BranchExchange::bx({{ }});
159 0xb: PredOp::clz({{
160 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
161 }});
162 }
163 0x2: decode OPCODE {
164 0x9: WarnUnimpl::bxj();
165 }
166 0x3: decode OPCODE {
167 0x9: BranchExchange::blx({{ }}, Link);
168 }
169 0x5: decode OPCODE {
170 0x8: WarnUnimpl::qadd();
171 0x9: WarnUnimpl::qsub();
172 0xa: WarnUnimpl::qdadd();
173 0xb: WarnUnimpl::qdsub();
174 }
175 0x8: decode OPCODE {
176 0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
177 0x9: WarnUnimpl::smlalbb();
178 0xa: WarnUnimpl::smlawb();
179 0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none);
180 }
181 0xa: decode OPCODE {
182 0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
183 0x9: smulwb({{
184 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16);
185 }}, none);
186 0xa: WarnUnimpl::smlaltb();
187 0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none);
188 }
189 0xc: decode OPCODE {
190 0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
191 0x9: WarnUnimpl::smlawt();
192 0xa: WarnUnimpl::smlalbt();
193 0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none);
194 }
195 0xe: decode OPCODE {
196 0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
197 0x9: smulwt({{
198 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16);
199 }}, none);
200 0xa: WarnUnimpl::smlaltt();
201 0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none);
202 }
203 }
204 }
205 }
206 0x1: decode IS_MISC {
207 0: decode OPCODE {
208 format DataImmOp {
209 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }});
210 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }});
211 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub);
212 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb);
213 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add);
214 0x5: adci({{
215 Rd = resTemp = Rn + rotated_imm + CondCodes<29:>;
216 }}, add);
217 0x6: sbci({{
218 Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>;
219 }}, sub);
220 0x7: rsci({{
221 Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>;
222 }}, rsb);
223 0x8: tsti({{ resTemp = Rn & rotated_imm; }});
224 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }});
225 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub);
226 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add);
227 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }});
228 0xd: movi({{ Rd = resTemp = rotated_imm; }});
229 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }});
230 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }});
231 }
232 }
233 1: decode OPCODE {
234 // The following two instructions aren't supposed to be defined
235 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
236 0x9: decode RN {
237 0: decode IMM {
238 0: PredImmOp::nop({{ ; }});
239 1: WarnUnimpl::yield();
240 2: WarnUnimpl::wfe();
241 3: WarnUnimpl::wfi();
242 4: WarnUnimpl::sev();
243 }
244 default: PredImmOp::msr_i_cpsr({{
245 uint32_t newCpsr =
246 cpsrWriteByInstr(Cpsr | CondCodes,
247 rotated_imm, RN, false);
248 Cpsr = ~CondCodesMask & newCpsr;
249 CondCodes = CondCodesMask & newCpsr;
250 }});
251 }
252 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
253 0xb: PredImmOp::msr_i_spsr({{
254 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
255 }});
256 }
257 }
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// The actual ARM ISA decoder
46// --------------------------
47// The following instructions are specified in the ARM ISA
48// Specification. Decoding closely follows the style specified
49// in the ARM ISA specification document starting with Table B.1 or 3-1
50//
51//
52
530: decode ENCODING {
54format DataOp {
55 0x0: decode SEVEN_AND_FOUR {
56 1: decode MISC_OPCODE {
57 0x9: decode PREPOST {
58 0: decode OPCODE {
59 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
60 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none);
61 0x2: WarnUnimpl::umall();
62 0x4: umull({{
63 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
64 Rd = (uint32_t)(resTemp & 0xffffffff);
65 Rn = (uint32_t)(resTemp >> 32);
66 }}, llbit);
67 0x5: smlal({{
68 resTemp = ((int64_t)Rm) * ((int64_t)Rs);
69 resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd);
70 Rd = (uint32_t)(resTemp & 0xffffffff);
71 Rn = (uint32_t)(resTemp >> 32);
72 }}, llbit);
73 0x6: smull({{
74 resTemp = ((int64_t)(int32_t)Rm)*
75 ((int64_t)(int32_t)Rs);
76 Rd = (int32_t)(resTemp & 0xffffffff);
77 Rn = (int32_t)(resTemp >> 32);
78 }}, llbit);
79 0x7: umlal({{
80 resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
81 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
82 Rd = (uint32_t)(resTemp & 0xffffffff);
83 Rn = (uint32_t)(resTemp >> 32);
84 }}, llbit);
85 }
86 1: decode PUBWL {
87 0x10: WarnUnimpl::swp();
88 0x14: WarnUnimpl::swpb();
89 0x18: WarnUnimpl::strex();
90 0x19: WarnUnimpl::ldrex();
91 }
92 }
93 format AddrMode3 {
94 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }},
95 load, {{ Rd = Mem.uh; }});
96 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0);
97 Rdo = bits(Mem.ud, 63, 32); }},
98 load, {{ Rd = Mem.sb; }});
99 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) |
100 (Rdo.ud << 32); }},
101 load, {{ Rd = Mem.sh; }});
102 }
103 }
104 0: decode IS_MISC {
105 0: decode OPCODE {
106 0x0: and({{ Rd = resTemp = Rn & op2; }});
107 0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
108 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
109 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
110 0x4: add({{ Rd = resTemp = Rn + op2; }}, add);
111 0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add);
112 0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub);
113 0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb);
114 0x8: tst({{ resTemp = Rn & op2; }});
115 0x9: teq({{ resTemp = Rn ^ op2; }});
116 0xa: cmp({{ resTemp = Rn - op2; }}, sub);
117 0xb: cmn({{ resTemp = Rn + op2; }}, add);
118 0xc: orr({{ Rd = resTemp = Rn | op2; }});
119 0xd: mov({{ Rd = resTemp = op2; }});
120 0xe: bic({{ Rd = resTemp = Rn & ~op2; }});
121 0xf: mvn({{ Rd = resTemp = ~op2; }});
122 }
123 1: decode MISC_OPCODE {
124 0x0: decode OPCODE {
125 0x8: PredOp::mrs_cpsr({{
126 Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
127 }});
128 0x9: decode USEIMM {
129 // The mask field is the same as the RN index.
130 0: PredOp::msr_cpsr_reg({{
131 uint32_t newCpsr =
132 cpsrWriteByInstr(Cpsr | CondCodes,
133 Rm, RN, false);
134 Cpsr = ~CondCodesMask & newCpsr;
135 CondCodes = CondCodesMask & newCpsr;
136 }});
137 1: PredImmOp::msr_cpsr_imm({{
138 uint32_t newCpsr =
139 cpsrWriteByInstr(Cpsr | CondCodes,
140 rotated_imm, RN, false);
141 Cpsr = ~CondCodesMask & newCpsr;
142 CondCodes = CondCodesMask & newCpsr;
143 }});
144 }
145 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
146 0xb: decode USEIMM {
147 // The mask field is the same as the RN index.
148 0: PredOp::msr_spsr_reg({{
149 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
150 }});
151 1: PredImmOp::msr_spsr_imm({{
152 Spsr = spsrWriteByInstr(Spsr, rotated_imm,
153 RN, false);
154 }});
155 }
156 }
157 0x1: decode OPCODE {
158 0x9: BranchExchange::bx({{ }});
159 0xb: PredOp::clz({{
160 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
161 }});
162 }
163 0x2: decode OPCODE {
164 0x9: WarnUnimpl::bxj();
165 }
166 0x3: decode OPCODE {
167 0x9: BranchExchange::blx({{ }}, Link);
168 }
169 0x5: decode OPCODE {
170 0x8: WarnUnimpl::qadd();
171 0x9: WarnUnimpl::qsub();
172 0xa: WarnUnimpl::qdadd();
173 0xb: WarnUnimpl::qdsub();
174 }
175 0x8: decode OPCODE {
176 0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
177 0x9: WarnUnimpl::smlalbb();
178 0xa: WarnUnimpl::smlawb();
179 0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none);
180 }
181 0xa: decode OPCODE {
182 0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
183 0x9: smulwb({{
184 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16);
185 }}, none);
186 0xa: WarnUnimpl::smlaltb();
187 0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none);
188 }
189 0xc: decode OPCODE {
190 0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
191 0x9: WarnUnimpl::smlawt();
192 0xa: WarnUnimpl::smlalbt();
193 0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none);
194 }
195 0xe: decode OPCODE {
196 0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
197 0x9: smulwt({{
198 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16);
199 }}, none);
200 0xa: WarnUnimpl::smlaltt();
201 0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none);
202 }
203 }
204 }
205 }
206 0x1: decode IS_MISC {
207 0: decode OPCODE {
208 format DataImmOp {
209 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }});
210 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }});
211 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub);
212 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb);
213 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add);
214 0x5: adci({{
215 Rd = resTemp = Rn + rotated_imm + CondCodes<29:>;
216 }}, add);
217 0x6: sbci({{
218 Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>;
219 }}, sub);
220 0x7: rsci({{
221 Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>;
222 }}, rsb);
223 0x8: tsti({{ resTemp = Rn & rotated_imm; }});
224 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }});
225 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub);
226 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add);
227 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }});
228 0xd: movi({{ Rd = resTemp = rotated_imm; }});
229 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }});
230 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }});
231 }
232 }
233 1: decode OPCODE {
234 // The following two instructions aren't supposed to be defined
235 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
236 0x9: decode RN {
237 0: decode IMM {
238 0: PredImmOp::nop({{ ; }});
239 1: WarnUnimpl::yield();
240 2: WarnUnimpl::wfe();
241 3: WarnUnimpl::wfi();
242 4: WarnUnimpl::sev();
243 }
244 default: PredImmOp::msr_i_cpsr({{
245 uint32_t newCpsr =
246 cpsrWriteByInstr(Cpsr | CondCodes,
247 rotated_imm, RN, false);
248 Cpsr = ~CondCodesMask & newCpsr;
249 CondCodes = CondCodesMask & newCpsr;
250 }});
251 }
252 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
253 0xb: PredImmOp::msr_i_spsr({{
254 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
255 }});
256 }
257 }
|
258 0x2: AddrMode2::addrMode2(Disp, disp);
| 258 0x2: AddrMode2::addrMode2(True, Disp, disp);
|
259 0x3: decode OPCODE_4 {
| 259 0x3: decode OPCODE_4 {
|
260 0: AddrMode2::addrMode2(Shift, Rm_Imm);
| 260 0: AddrMode2::addrMode2(False, Shift, Rm_Imm);
|
261 1: decode MEDIA_OPCODE {
262 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
263 0x8: decode MISC_OPCODE {
264 0x1, 0x9: WarnUnimpl::pkhbt();
265 0x7: WarnUnimpl::sxtab16();
266 0xb: WarnUnimpl::sel();
267 0x5, 0xd: WarnUnimpl::pkhtb();
268 0x3: WarnUnimpl::sign_zero_extend_add();
269 }
270 0xa, 0xb: decode SHIFT {
271 0x0, 0x2: WarnUnimpl::ssat();
272 0x1: WarnUnimpl::ssat16();
273 }
274 0xe, 0xf: decode SHIFT {
275 0x0, 0x2: WarnUnimpl::usat();
276 0x1: WarnUnimpl::usat16();
277 }
278 0x10: decode RN {
279 0xf: decode MISC_OPCODE {
280 0x1: WarnUnimpl::smuad();
281 0x3: WarnUnimpl::smuadx();
282 0x5: WarnUnimpl::smusd();
283 0x7: WarnUnimpl::smusdx();
284 }
285 default: decode MISC_OPCODE {
286 0x1: WarnUnimpl::smlad();
287 0x3: WarnUnimpl::smladx();
288 0x5: WarnUnimpl::smlsd();
289 0x7: WarnUnimpl::smlsdx();
290 }
291 }
292 0x14: decode MISC_OPCODE {
293 0x1: WarnUnimpl::smlald();
294 0x3: WarnUnimpl::smlaldx();
295 0x5: WarnUnimpl::smlsld();
296 0x7: WarnUnimpl::smlsldx();
297 }
298 0x15: decode RN {
299 0xf: decode MISC_OPCODE {
300 0x1: WarnUnimpl::smmul();
301 0x3: WarnUnimpl::smmulr();
302 }
303 default: decode MISC_OPCODE {
304 0x1: WarnUnimpl::smmla();
305 0x3: WarnUnimpl::smmlar();
306 0xd: WarnUnimpl::smmls();
307 0xf: WarnUnimpl::smmlsr();
308 }
309 }
310 0x18: decode RN {
311 0xf: WarnUnimpl::usada8();
312 default: WarnUnimpl::usad8();
313 }
314 }
315 }
316 0x4: decode PUSWL {
317 // Right now we only handle cases when S (PSRUSER) is not set
318 default: ArmMacroStore::ldmstm({{ }});
319 }
320 0x5: decode OPCODE_24 {
321 // Branch (and Link) Instructions
322 0: Branch::b({{ }});
323 1: Branch::bl({{ }}, Link);
324 }
325 0x6: decode CPNUM {
326 0x1: decode PUNWL {
327 0x02,0x0a: decode OPCODE_15 {
328 0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf;
329 Rn = Rn + disp8; }},
330 {{ EA = Rn; }});
331 1: ArmMacroFPAOp::stfd_({{ }});
332 }
333 0x03,0x0b: decode OPCODE_15 {
334 0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf;
335 Rn = Rn + disp8; }},
336 {{ EA = Rn; }});
337 1: ArmMacroFPAOp::ldfd_({{ }});
338 }
339 0x06,0x0e: decode OPCODE_15 {
340 0: ArmMacroFPAOp::stfe_nw({{ }});
341 }
342 0x07,0x0f: decode OPCODE_15 {
343 0: ArmMacroFPAOp::ldfe_nw({{ }});
344 }
345 0x10,0x18: decode OPCODE_15 {
346 0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }},
347 {{ EA = Rn + disp8; }});
348 1: ArmMacroFPAOp::stfd_p({{ }});
349 }
350 0x11,0x19: decode OPCODE_15 {
351 0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }},
352 {{ EA = Rn + disp8; }});
353 1: ArmMacroFPAOp::ldfd_p({{ }});
354 }
355 0x12,0x1a: decode OPCODE_15 {
356 0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf;
357 Rn = Rn + disp8; }},
358 {{ EA = Rn + disp8; }});
359 1: ArmMacroFPAOp::stfd_pw({{ }});
360 }
361 0x13,0x1b: decode OPCODE_15 {
362 0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf;
363 Rn = Rn + disp8; }},
364 {{ EA = Rn + disp8; }});
365 1: ArmMacroFPAOp::ldfd_pw({{ }});
366 }
367 0x14,0x1c: decode OPCODE_15 {
368 0: ArmMacroFPAOp::stfe_pn({{ }});
369 }
370 0x15,0x1d: decode OPCODE_15 {
371 0: ArmMacroFPAOp::ldfe_pn({{ }});
372 }
373 0x16,0x1e: decode OPCODE_15 {
374 0: ArmMacroFPAOp::stfe_pnw({{ }});
375 }
376 0x17,0x1f: decode OPCODE_15 {
377 0: ArmMacroFPAOp::ldfe_pnw({{ }});
378 }
379 }
380 0x2: decode PUNWL {
381 // could really just decode as a single instruction
382 0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }});
383 0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }});
384 0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }});
385 0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }});
386 0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }});
387 0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }});
388 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }});
389 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }});
390 }
391 0xb: decode LOADOP {
392 0x0: WarnUnimpl::fstmx();
393 0x1: WarnUnimpl::fldmx();
394 }
395 }
396 0x7: decode OPCODE_24 {
397 0: decode OPCODE_4 {
398 0: decode CPNUM {
399 0xa, 0xb: decode OPCODE_23_20 {
400##include "vfp.isa"
401 }
402 } // CPNUM
403 1: decode CPNUM { // 27-24=1110,4 ==1
404 1: decode OPCODE_15_12 {
405 format FloatOp {
406 0xf: decode OPCODE_23_21 {
407 format FloatCmp {
408 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
409 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
410 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
411 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
412 }
413 }
414 default: decode OPCODE_23_20 {
415 0x0: decode OPCODE_7 {
416 0: flts({{ Fn.sf = (float) Rd.sw; }});
417 1: fltd({{ Fn.df = (double) Rd.sw; }});
418 }
419 0x1: decode OPCODE_7 {
420 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
421 1: fixd({{ Rd = (uint32_t) Fm.df; }});
422 }
423 0x2: wfs({{ Fpsr = Rd; }});
424 0x3: rfs({{ Rd = Fpsr; }});
425 0x4: FailUnimpl::wfc();
426 0x5: FailUnimpl::rfc();
427 }
428 } // format FloatOp
429 }
430 0xa: decode MISC_OPCODE {
431 0x1: decode MEDIA_OPCODE {
432 0xf: decode RN {
433 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
434 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
435 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
436 }
437 0xe: decode RN {
438 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
439 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
440 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
441 }
442 } // MEDIA_OPCODE (MISC_OPCODE 0x1)
443 } // MISC_OPCODE (CPNUM 0xA)
444 0xf: decode RN {
445 // Barrriers, Cache Maintence, NOPS
446 7: decode OPCODE_23_21 {
447 0: decode RM {
448 0: decode OPC2 {
449 4: decode OPCODE_20 {
450 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
451 }
452 }
453 1: WarnUnimpl::cp15_cache_maint();
454 4: WarnUnimpl::cp15_par();
455 5: decode OPC2 {
456 0,1: WarnUnimpl::cp15_cache_maint2();
457 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
458 6,7: WarnUnimpl::cp15_bp_maint();
459 }
460 6: WarnUnimpl::cp15_cache_maint3();
461 8: WarnUnimpl::cp15_va_to_pa();
462 10: decode OPC2 {
463 1,2: WarnUnimpl::cp15_cache_maint3();
464 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
465 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
466 }
467 11: WarnUnimpl::cp15_cache_maint4();
468 13: decode OPC2 {
469 1: decode OPCODE_20 {
470 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
471 }
472 }
473 14: WarnUnimpl::cp15_cache_maint5();
474 } // RM
475 } // OPCODE_23_21 CR
476
477 // Thread ID and context ID registers
478 // Thread ID register needs cheaper access than miscreg
479 13: WarnUnimpl::mcr_mrc_cp15_c7();
480
481 // All the rest
482 default: decode OPCODE_20 {
483 0: PredOp::mcr_cp15({{
484 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
485 }});
486 1: PredOp::mrc_cp15({{
487 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
488 }});
489 }
490 } // RN
491 } // CPNUM (OP4 == 1)
492 } //OPCODE_4
493
494#if FULL_SYSTEM
495 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
496#else
497 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode))
498 {
499 if (IMMED_23_0)
500 xc->syscall(IMMED_23_0);
501 else
502 xc->syscall(R7);
503 }
504 }});
505#endif // FULL_SYSTEM
506 } // OPCODE_24
507
508}
509}
510
| 261 1: decode MEDIA_OPCODE {
262 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
263 0x8: decode MISC_OPCODE {
264 0x1, 0x9: WarnUnimpl::pkhbt();
265 0x7: WarnUnimpl::sxtab16();
266 0xb: WarnUnimpl::sel();
267 0x5, 0xd: WarnUnimpl::pkhtb();
268 0x3: WarnUnimpl::sign_zero_extend_add();
269 }
270 0xa, 0xb: decode SHIFT {
271 0x0, 0x2: WarnUnimpl::ssat();
272 0x1: WarnUnimpl::ssat16();
273 }
274 0xe, 0xf: decode SHIFT {
275 0x0, 0x2: WarnUnimpl::usat();
276 0x1: WarnUnimpl::usat16();
277 }
278 0x10: decode RN {
279 0xf: decode MISC_OPCODE {
280 0x1: WarnUnimpl::smuad();
281 0x3: WarnUnimpl::smuadx();
282 0x5: WarnUnimpl::smusd();
283 0x7: WarnUnimpl::smusdx();
284 }
285 default: decode MISC_OPCODE {
286 0x1: WarnUnimpl::smlad();
287 0x3: WarnUnimpl::smladx();
288 0x5: WarnUnimpl::smlsd();
289 0x7: WarnUnimpl::smlsdx();
290 }
291 }
292 0x14: decode MISC_OPCODE {
293 0x1: WarnUnimpl::smlald();
294 0x3: WarnUnimpl::smlaldx();
295 0x5: WarnUnimpl::smlsld();
296 0x7: WarnUnimpl::smlsldx();
297 }
298 0x15: decode RN {
299 0xf: decode MISC_OPCODE {
300 0x1: WarnUnimpl::smmul();
301 0x3: WarnUnimpl::smmulr();
302 }
303 default: decode MISC_OPCODE {
304 0x1: WarnUnimpl::smmla();
305 0x3: WarnUnimpl::smmlar();
306 0xd: WarnUnimpl::smmls();
307 0xf: WarnUnimpl::smmlsr();
308 }
309 }
310 0x18: decode RN {
311 0xf: WarnUnimpl::usada8();
312 default: WarnUnimpl::usad8();
313 }
314 }
315 }
316 0x4: decode PUSWL {
317 // Right now we only handle cases when S (PSRUSER) is not set
318 default: ArmMacroStore::ldmstm({{ }});
319 }
320 0x5: decode OPCODE_24 {
321 // Branch (and Link) Instructions
322 0: Branch::b({{ }});
323 1: Branch::bl({{ }}, Link);
324 }
325 0x6: decode CPNUM {
326 0x1: decode PUNWL {
327 0x02,0x0a: decode OPCODE_15 {
328 0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf;
329 Rn = Rn + disp8; }},
330 {{ EA = Rn; }});
331 1: ArmMacroFPAOp::stfd_({{ }});
332 }
333 0x03,0x0b: decode OPCODE_15 {
334 0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf;
335 Rn = Rn + disp8; }},
336 {{ EA = Rn; }});
337 1: ArmMacroFPAOp::ldfd_({{ }});
338 }
339 0x06,0x0e: decode OPCODE_15 {
340 0: ArmMacroFPAOp::stfe_nw({{ }});
341 }
342 0x07,0x0f: decode OPCODE_15 {
343 0: ArmMacroFPAOp::ldfe_nw({{ }});
344 }
345 0x10,0x18: decode OPCODE_15 {
346 0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }},
347 {{ EA = Rn + disp8; }});
348 1: ArmMacroFPAOp::stfd_p({{ }});
349 }
350 0x11,0x19: decode OPCODE_15 {
351 0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }},
352 {{ EA = Rn + disp8; }});
353 1: ArmMacroFPAOp::ldfd_p({{ }});
354 }
355 0x12,0x1a: decode OPCODE_15 {
356 0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf;
357 Rn = Rn + disp8; }},
358 {{ EA = Rn + disp8; }});
359 1: ArmMacroFPAOp::stfd_pw({{ }});
360 }
361 0x13,0x1b: decode OPCODE_15 {
362 0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf;
363 Rn = Rn + disp8; }},
364 {{ EA = Rn + disp8; }});
365 1: ArmMacroFPAOp::ldfd_pw({{ }});
366 }
367 0x14,0x1c: decode OPCODE_15 {
368 0: ArmMacroFPAOp::stfe_pn({{ }});
369 }
370 0x15,0x1d: decode OPCODE_15 {
371 0: ArmMacroFPAOp::ldfe_pn({{ }});
372 }
373 0x16,0x1e: decode OPCODE_15 {
374 0: ArmMacroFPAOp::stfe_pnw({{ }});
375 }
376 0x17,0x1f: decode OPCODE_15 {
377 0: ArmMacroFPAOp::ldfe_pnw({{ }});
378 }
379 }
380 0x2: decode PUNWL {
381 // could really just decode as a single instruction
382 0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }});
383 0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }});
384 0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }});
385 0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }});
386 0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }});
387 0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }});
388 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }});
389 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }});
390 }
391 0xb: decode LOADOP {
392 0x0: WarnUnimpl::fstmx();
393 0x1: WarnUnimpl::fldmx();
394 }
395 }
396 0x7: decode OPCODE_24 {
397 0: decode OPCODE_4 {
398 0: decode CPNUM {
399 0xa, 0xb: decode OPCODE_23_20 {
400##include "vfp.isa"
401 }
402 } // CPNUM
403 1: decode CPNUM { // 27-24=1110,4 ==1
404 1: decode OPCODE_15_12 {
405 format FloatOp {
406 0xf: decode OPCODE_23_21 {
407 format FloatCmp {
408 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
409 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
410 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
411 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
412 }
413 }
414 default: decode OPCODE_23_20 {
415 0x0: decode OPCODE_7 {
416 0: flts({{ Fn.sf = (float) Rd.sw; }});
417 1: fltd({{ Fn.df = (double) Rd.sw; }});
418 }
419 0x1: decode OPCODE_7 {
420 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
421 1: fixd({{ Rd = (uint32_t) Fm.df; }});
422 }
423 0x2: wfs({{ Fpsr = Rd; }});
424 0x3: rfs({{ Rd = Fpsr; }});
425 0x4: FailUnimpl::wfc();
426 0x5: FailUnimpl::rfc();
427 }
428 } // format FloatOp
429 }
430 0xa: decode MISC_OPCODE {
431 0x1: decode MEDIA_OPCODE {
432 0xf: decode RN {
433 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
434 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
435 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
436 }
437 0xe: decode RN {
438 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
439 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
440 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
441 }
442 } // MEDIA_OPCODE (MISC_OPCODE 0x1)
443 } // MISC_OPCODE (CPNUM 0xA)
444 0xf: decode RN {
445 // Barrriers, Cache Maintence, NOPS
446 7: decode OPCODE_23_21 {
447 0: decode RM {
448 0: decode OPC2 {
449 4: decode OPCODE_20 {
450 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
451 }
452 }
453 1: WarnUnimpl::cp15_cache_maint();
454 4: WarnUnimpl::cp15_par();
455 5: decode OPC2 {
456 0,1: WarnUnimpl::cp15_cache_maint2();
457 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
458 6,7: WarnUnimpl::cp15_bp_maint();
459 }
460 6: WarnUnimpl::cp15_cache_maint3();
461 8: WarnUnimpl::cp15_va_to_pa();
462 10: decode OPC2 {
463 1,2: WarnUnimpl::cp15_cache_maint3();
464 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
465 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
466 }
467 11: WarnUnimpl::cp15_cache_maint4();
468 13: decode OPC2 {
469 1: decode OPCODE_20 {
470 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
471 }
472 }
473 14: WarnUnimpl::cp15_cache_maint5();
474 } // RM
475 } // OPCODE_23_21 CR
476
477 // Thread ID and context ID registers
478 // Thread ID register needs cheaper access than miscreg
479 13: WarnUnimpl::mcr_mrc_cp15_c7();
480
481 // All the rest
482 default: decode OPCODE_20 {
483 0: PredOp::mcr_cp15({{
484 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
485 }});
486 1: PredOp::mrc_cp15({{
487 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
488 }});
489 }
490 } // RN
491 } // CPNUM (OP4 == 1)
492 } //OPCODE_4
493
494#if FULL_SYSTEM
495 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
496#else
497 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode))
498 {
499 if (IMMED_23_0)
500 xc->syscall(IMMED_23_0);
501 else
502 xc->syscall(R7);
503 }
504 }});
505#endif // FULL_SYSTEM
506 } // OPCODE_24
507
508}
509}
510
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