arm.isa (7334:5e8dcb57096f) | arm.isa (7344:82a4e24e7fad) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 53 unchanged lines hidden (view full) --- 62 } 63 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 64 } 65 0: decode IS_MISC { 66 0: ArmDataProcReg::armDataProcReg(); 67 1: decode OPCODE_7 { 68 0x0: decode MISC_OPCODE { 69 0x0: ArmMsrMrs::armMsrMrs(); | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 53 unchanged lines hidden (view full) --- 62 } 63 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 64 } 65 0: decode IS_MISC { 66 0: ArmDataProcReg::armDataProcReg(); 67 1: decode OPCODE_7 { 68 0x0: decode MISC_OPCODE { 69 0x0: ArmMsrMrs::armMsrMrs(); |
70 0x1: ArmBxClz::armBxClz(); 71 0x2: decode OPCODE { 72 0x9: WarnUnimpl::bxj(); 73 } | 70 // bxj unimplemented, treated as bx 71 0x1,0x2: ArmBxClz::armBxClz(); |
74 0x3: decode OPCODE { 75 0x9: ArmBlxReg::armBlxReg(); 76 } 77 0x5: ArmSatAddSub::armSatAddSub(); 78 } 79 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 80 } 81 } --- 92 unchanged lines hidden --- | 72 0x3: decode OPCODE { 73 0x9: ArmBlxReg::armBlxReg(); 74 } 75 0x5: ArmSatAddSub::armSatAddSub(); 76 } 77 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 78 } 79 } --- 92 unchanged lines hidden --- |