1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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50//
51//
52
530: decode ENCODING {
54format DataOp {
55 0x0: decode SEVEN_AND_FOUR {
56 1: decode MISC_OPCODE {
57 0x9: decode PREPOST {
58 0: ArmMultAndMultAcc::armMultAndMultAcc();
59 1: decode PUBWL {
60 0x10: WarnUnimpl::swp();
61 0x14: WarnUnimpl::swpb();
62 0x18: WarnUnimpl::strex();
63 0x19: WarnUnimpl::ldrex();
64 }
65 }
66 0xb, 0xd, 0xf: AddrMode3::addrMode3();
67 }
68 0: decode IS_MISC {
69 0: ArmDataProcReg::armDataProcReg();
70 1: decode OPCODE_7 {
71 0x0: decode MISC_OPCODE {
72 0x0: decode OPCODE {
73 0x8: PredOp::mrs_cpsr({{
74 Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
75 }});
76 0x9: decode USEIMM {
77 // The mask field is the same as the RN index.
78 0: PredOp::msr_cpsr_reg({{
79 uint32_t newCpsr =
80 cpsrWriteByInstr(Cpsr | CondCodes,
81 Rm, RN, false);
82 Cpsr = ~CondCodesMask & newCpsr;
83 CondCodes = CondCodesMask & newCpsr;
84 }});
85 1: PredImmOp::msr_cpsr_imm({{
86 uint32_t newCpsr =
87 cpsrWriteByInstr(Cpsr | CondCodes,
88 rotated_imm, RN, false);
89 Cpsr = ~CondCodesMask & newCpsr;
90 CondCodes = CondCodesMask & newCpsr;
91 }});
92 }
93 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
94 0xb: decode USEIMM {
95 // The mask field is the same as the RN index.
96 0: PredOp::msr_spsr_reg({{
97 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
98 }});
99 1: PredImmOp::msr_spsr_imm({{
100 Spsr = spsrWriteByInstr(Spsr, rotated_imm,
101 RN, false);
102 }});
103 }
104 }
105 0x1: decode OPCODE {
106 0x9: ArmBx::armBx();
107 0xb: PredOp::clz({{
108 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
109 }});
110 }
111 0x2: decode OPCODE {
112 0x9: WarnUnimpl::bxj();
113 }
114 0x3: decode OPCODE {
115 0x9: ArmBlxReg::armBlxReg();
116 }
117 0x5: decode OPCODE {
118 0x8: WarnUnimpl::qadd();
119 0x9: WarnUnimpl::qsub();
120 0xa: WarnUnimpl::qdadd();
121 0xb: WarnUnimpl::qdsub();
122 }
123 }
124 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
125 }
126 }
127 }
128 0x1: decode IS_MISC {
129 0: ArmDataProcImm::armDataProcImm();
130 1: decode OPCODE {
131 // The following two instructions aren't supposed to be defined
132 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});

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150 0xb: PredImmOp::msr_i_spsr({{
151 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
152 }});
153 }
154 }
155 0x2: AddrMode2::addrMode2(True);
156 0x3: decode OPCODE_4 {
157 0: AddrMode2::addrMode2(False);
158 1: decode OPCODE_24_23 {
159 0x0: WarnUnimpl::parallel_add_subtract_instructions();
160 0x1: decode MEDIA_OPCODE {
161 0x8: decode MISC_OPCODE {
162 0x1, 0x9: WarnUnimpl::pkhbt();
163 0x7: WarnUnimpl::sxtab16();
164 0xb: WarnUnimpl::sel();
165 0x5, 0xd: WarnUnimpl::pkhtb();
166 0x3: WarnUnimpl::sign_zero_extend_add();
167 }
168 0xa, 0xb: decode SHIFT {
169 0x0, 0x2: WarnUnimpl::ssat();
170 0x1: WarnUnimpl::ssat16();
171 }
172 0xe, 0xf: decode SHIFT {
173 0x0, 0x2: WarnUnimpl::usat();
174 0x1: WarnUnimpl::usat16();
175 }
176 }
177 0x2: ArmSignedMultiplies::armSignedMultiplies();
178 0x3: decode MEDIA_OPCODE {
179 0x18: decode RN {
180 0xf: WarnUnimpl::usada8();
181 default: WarnUnimpl::usad8();
182 }
183 }
184 }
185 }
186 0x4: ArmMacroMem::armMacroMem();
187 0x5: decode OPCODE_24 {
188 0: ArmBBlxImm::armBBlxImm();
189 1: ArmBlBlxImm::armBlBlxImm();
190 }
191 0x6: decode CPNUM {

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