isa.hh (8232:b28d06a175be) isa.hh (9384:877293183bdf)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_ARM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/types.hh"
49#include "debug/Checkpoint.hh"
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_ARM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/types.hh"
49#include "debug/Checkpoint.hh"
50#include "sim/sim_object.hh"
50
51
52struct ArmISAParams;
51class ThreadContext;
52class Checkpoint;
53class EventManager;
54
55namespace ArmISA
56{
53class ThreadContext;
54class Checkpoint;
55class EventManager;
56
57namespace ArmISA
58{
57 class ISA
59 class ISA : public SimObject
58 {
59 protected:
60 MiscReg miscRegs[NumMiscRegs];
61 const IntRegIndex *intRegMap;
62
63 void
64 updateRegMap(CPSR cpsr)
65 {

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187 const std::string &section)
188 {
189 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
190 UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
191 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
192 updateRegMap(tmp_cpsr);
193 }
194
60 {
61 protected:
62 MiscReg miscRegs[NumMiscRegs];
63 const IntRegIndex *intRegMap;
64
65 void
66 updateRegMap(CPSR cpsr)
67 {

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189 const std::string &section)
190 {
191 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
192 UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
193 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
194 updateRegMap(tmp_cpsr);
195 }
196
195 ISA()
196 {
197 SCTLR sctlr;
198 sctlr = 0;
199 miscRegs[MISCREG_SCTLR_RST] = sctlr;
197 typedef ArmISAParams Params;
200
198
201 clear();
202 }
199 const Params *params() const;
200
201 ISA(Params *p);
203 };
204}
205
206#endif
202 };
203}
204
205#endif