isa.hh (7614:763e836c0e70) isa.hh (7733:08d6a773d1b6)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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173 break;
174 }
175 return spsr_idx;
176 }
177 return reg;
178 }
179
180 void serialize(EventManager *em, std::ostream &os)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 164 unchanged lines hidden (view full) ---

173 break;
174 }
175 return spsr_idx;
176 }
177 return reg;
178 }
179
180 void serialize(EventManager *em, std::ostream &os)
181 {}
181 {
182 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
183 SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
184 }
182 void unserialize(EventManager *em, Checkpoint *cp,
183 const std::string &section)
185 void unserialize(EventManager *em, Checkpoint *cp,
186 const std::string &section)
184 {}
187 {
188 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
189 UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
190 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
191 updateRegMap(tmp_cpsr);
192 }
185
186 ISA()
187 {
188 SCTLR sctlr;
189 sctlr = 0;
190 miscRegs[MISCREG_SCTLR_RST] = sctlr;
191
192 clear();
193 }
194 };
195}
196
197#endif
193
194 ISA()
195 {
196 SCTLR sctlr;
197 sctlr = 0;
198 miscRegs[MISCREG_SCTLR_RST] = sctlr;
199
200 clear();
201 }
202 };
203}
204
205#endif