isa.hh (7406:ddc26bd4ea7d) isa.hh (7427:1267715c2112)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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86 intRegMap = IntRegUndMap;
87 break;
88 default:
89 panic("Unrecognized mode setting in CPSR.\n");
90 }
91 }
92
93 public:
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 77 unchanged lines hidden (view full) ---

86 intRegMap = IntRegUndMap;
87 break;
88 default:
89 panic("Unrecognized mode setting in CPSR.\n");
90 }
91 }
92
93 public:
94 void clear()
95 {
96 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
94 void clear();
97
95
98 memset(miscRegs, 0, sizeof(miscRegs));
99 CPSR cpsr = 0;
100 cpsr.mode = MODE_USER;
101 miscRegs[MISCREG_CPSR] = cpsr;
102 updateRegMap(cpsr);
103
104 SCTLR sctlr = 0;
105 sctlr.nmfi = (bool)sctlr_rst.nmfi;
106 sctlr.v = (bool)sctlr_rst.v;
107 sctlr.u = 1;
108 sctlr.xp = 1;
109 sctlr.rao2 = 1;
110 sctlr.rao3 = 1;
111 sctlr.rao4 = 1;
112 miscRegs[MISCREG_SCTLR] = sctlr;
113 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
114
115
116 /*
117 * Technically this should be 0, but we don't support those
118 * settings.
119 */
120 CPACR cpacr = 0;
121 // Enable CP 10, 11
122 cpacr.cp10 = 0x3;
123 cpacr.cp11 = 0x3;
124 miscRegs[MISCREG_CPACR] = cpacr;
125
126 /* Start with an event in the mailbox */
127 miscRegs[MISCREG_SEV_MAILBOX] = 1;
128
129 /*
130 * Implemented = '5' from "M5",
131 * Variant = 0,
132 */
133 miscRegs[MISCREG_MIDR] =
134 (0x35 << 24) | //Implementor is '5' from "M5"
135 (0 << 20) | //Variant
136 (0xf << 16) | //Architecture from CPUID scheme
137 (0 << 4) | //Primary part number
138 (0 << 0) | //Revision
139 0;
140
141 // Separate Instruction and Data TLBs.
142 miscRegs[MISCREG_TLBTR] = 1;
143
144 MVFR0 mvfr0 = 0;
145 mvfr0.advSimdRegisters = 2;
146 mvfr0.singlePrecision = 2;
147 mvfr0.doublePrecision = 2;
148 mvfr0.vfpExceptionTrapping = 0;
149 mvfr0.divide = 1;
150 mvfr0.squareRoot = 1;
151 mvfr0.shortVectors = 1;
152 mvfr0.roundingModes = 1;
153 miscRegs[MISCREG_MVFR0] = mvfr0;
154
155 MVFR1 mvfr1 = 0;
156 mvfr1.flushToZero = 1;
157 mvfr1.defaultNaN = 1;
158 mvfr1.advSimdLoadStore = 1;
159 mvfr1.advSimdInteger = 1;
160 mvfr1.advSimdSinglePrecision = 1;
161 mvfr1.advSimdHalfPrecision = 1;
162 mvfr1.vfpHalfPrecision = 1;
163 miscRegs[MISCREG_MVFR1] = mvfr1;
164
165 miscRegs[MISCREG_MPIDR] = 0;
166
167 //XXX We need to initialize the rest of the state.
168 }
169
170 MiscReg readMiscRegNoEffect(int misc_reg);
96 MiscReg readMiscRegNoEffect(int misc_reg);
171
172 MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
97 MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
173
174 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
98 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
175
176 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
177
178 int
179 flattenIntIndex(int reg)
180 {
181 assert(reg >= 0);
182 if (reg < NUM_ARCH_INTREGS) {
183 return intRegMap[reg];

--- 51 unchanged lines hidden --- 		99 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
100
101 int
102 flattenIntIndex(int reg)
103 {
104 assert(reg >= 0);
105 if (reg < NUM_ARCH_INTREGS) {
106 return intRegMap[reg];

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