isa.hh (7393:8330b0b08daa) isa.hh (7400:f6c9b27c4dbe)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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87 default:
88 panic("Unrecognized mode setting in CPSR.\n");
89 }
90 }
91
92 public:
93 void clear()
94 {
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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87 default:
88 panic("Unrecognized mode setting in CPSR.\n");
89 }
90 }
91
92 public:
93 void clear()
94 {
95 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
96
95 memset(miscRegs, 0, sizeof(miscRegs));
96 CPSR cpsr = 0;
97 cpsr.mode = MODE_USER;
98 miscRegs[MISCREG_CPSR] = cpsr;
99 updateRegMap(cpsr);
100
101 SCTLR sctlr = 0;
97 memset(miscRegs, 0, sizeof(miscRegs));
98 CPSR cpsr = 0;
99 cpsr.mode = MODE_USER;
100 miscRegs[MISCREG_CPSR] = cpsr;
101 updateRegMap(cpsr);
102
103 SCTLR sctlr = 0;
102 sctlr.nmfi = 1;
104 sctlr.nmfi = (bool)sctlr_rst.nmfi;
105 sctlr.v = (bool)sctlr_rst.v;
106 sctlr.u = 1;
103 sctlr.rao1 = 1;
104 sctlr.rao2 = 1;
105 sctlr.rao3 = 1;
106 sctlr.rao4 = 1;
107 miscRegs[MISCREG_SCTLR] = sctlr;
107 sctlr.rao1 = 1;
108 sctlr.rao2 = 1;
109 sctlr.rao3 = 1;
110 sctlr.rao4 = 1;
111 miscRegs[MISCREG_SCTLR] = sctlr;
112 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
108
113
114
109 /*
110 * Technically this should be 0, but we don't support those
111 * settings.
112 */
113 CPACR cpacr = 0;
114 // Enable CP 10, 11
115 cpacr.cp10 = 0x3;
116 cpacr.cp11 = 0x3;

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322 break;
323 case MISCREG_FPEXC:
324 {
325 const uint32_t fpexcMask = 0x60000000;
326 newVal = (newVal & fpexcMask) |
327 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
328 }
329 break;
115 /*
116 * Technically this should be 0, but we don't support those
117 * settings.
118 */
119 CPACR cpacr = 0;
120 // Enable CP 10, 11
121 cpacr.cp10 = 0x3;
122 cpacr.cp11 = 0x3;

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328 break;
329 case MISCREG_FPEXC:
330 {
331 const uint32_t fpexcMask = 0x60000000;
332 newVal = (newVal & fpexcMask) |
333 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
334 }
335 break;
336 case MISCREG_SCTLR:
337 {
338 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
339 SCTLR new_sctlr = newVal;
340 new_sctlr.nmfi = (bool)sctlr.nmfi;
341 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
342 return;
343 }
330 case MISCREG_TLBTR:
331 case MISCREG_MVFR0:
332 case MISCREG_MVFR1:
333 case MISCREG_MPIDR:
334 case MISCREG_FPSID:
335 return;
336 }
344 case MISCREG_TLBTR:
345 case MISCREG_MVFR0:
346 case MISCREG_MVFR1:
347 case MISCREG_MPIDR:
348 case MISCREG_FPSID:
349 return;
350 }
337 return setMiscRegNoEffect(misc_reg, newVal);
351 setMiscRegNoEffect(misc_reg, newVal);
338 }
339
340 int
341 flattenIntIndex(int reg)
342 {
343 assert(reg >= 0);
344 if (reg < NUM_ARCH_INTREGS) {
345 return intRegMap[reg];

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379 void serialize(EventManager *em, std::ostream &os)
380 {}
381 void unserialize(EventManager *em, Checkpoint *cp,
382 const std::string &section)
383 {}
384
385 ISA()
386 {
352 }
353
354 int
355 flattenIntIndex(int reg)
356 {
357 assert(reg >= 0);
358 if (reg < NUM_ARCH_INTREGS) {
359 return intRegMap[reg];

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393 void serialize(EventManager *em, std::ostream &os)
394 {}
395 void unserialize(EventManager *em, Checkpoint *cp,
396 const std::string &section)
397 {}
398
399 ISA()
400 {
401 SCTLR sctlr;
402 sctlr = 0;
403 miscRegs[MISCREG_SCTLR_RST] = sctlr;
404
387 clear();
388 }
389 };
390}
391
392#endif
405 clear();
406 }
407 };
408}
409
410#endif