isa.hh (7354:732369e36c02) isa.hh (7383:0edb04052953)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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129 (0xf << 16) | //Architecture from CPUID scheme
130 (0 << 4) | //Primary part number
131 (0 << 0) | //Revision
132 0;
133
134 // Separate Instruction and Data TLBs.
135 miscRegs[MISCREG_TLBTR] = 1;
136
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 120 unchanged lines hidden (view full) ---

129 (0xf << 16) | //Architecture from CPUID scheme
130 (0 << 4) | //Primary part number
131 (0 << 0) | //Revision
132 0;
133
134 // Separate Instruction and Data TLBs.
135 miscRegs[MISCREG_TLBTR] = 1;
136
137 MVFR0 mvfr0 = 0;
138 mvfr0.advSimdRegisters = 2;
139 mvfr0.singlePrecision = 2;
140 mvfr0.doublePrecision = 2;
141 mvfr0.vfpExceptionTrapping = 0;
142 mvfr0.divide = 1;
143 mvfr0.squareRoot = 1;
144 mvfr0.shortVectors = 1;
145 mvfr0.roundingModes = 1;
146 miscRegs[MISCREG_MVFR0] = mvfr0;
147
148 MVFR1 mvfr1 = 0;
149 mvfr1.flushToZero = 1;
150 mvfr1.defaultNaN = 1;
151 mvfr1.advSimdLoadStore = 1;
152 mvfr1.advSimdInteger = 1;
153 mvfr1.advSimdSinglePrecision = 1;
154 mvfr1.advSimdHalfPrecision = 1;
155 mvfr1.vfpHalfPrecision = 1;
156 miscRegs[MISCREG_MVFR1] = mvfr1;
157
137 //XXX We need to initialize the rest of the state.
138 }
139
140 MiscReg
141 readMiscRegNoEffect(int misc_reg)
142 {
143 assert(misc_reg < NumMiscRegs);
144 if (misc_reg == MISCREG_SPSR) {

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268 }
269 newVal = newCpacr;
270 }
271 break;
272 case MISCREG_CSSELR:
273 warn("The csselr register isn't implemented.\n");
274 break;
275 case MISCREG_TLBTR:
158 //XXX We need to initialize the rest of the state.
159 }
160
161 MiscReg
162 readMiscRegNoEffect(int misc_reg)
163 {
164 assert(misc_reg < NumMiscRegs);
165 if (misc_reg == MISCREG_SPSR) {

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289 }
290 newVal = newCpacr;
291 }
292 break;
293 case MISCREG_CSSELR:
294 warn("The csselr register isn't implemented.\n");
295 break;
296 case MISCREG_TLBTR:
297 case MISCREG_MVFR0:
298 case MISCREG_MVFR1:
276 return;
277 }
278 return setMiscRegNoEffect(misc_reg, newVal);
279 }
280
281 int
282 flattenIntIndex(int reg)
283 {

--- 50 unchanged lines hidden --- 		299 return;
300 }
301 return setMiscRegNoEffect(misc_reg, newVal);
302 }
303
304 int
305 flattenIntIndex(int reg)
306 {

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