isa.hh (7351:d90afcb8724e) isa.hh (7354:732369e36c02)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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126 miscRegs[MISCREG_MIDR] =
127 (0x35 << 24) | //Implementor is '5' from "M5"
128 (0 << 20) | //Variant
129 (0xf << 16) | //Architecture from CPUID scheme
130 (0 << 4) | //Primary part number
131 (0 << 0) | //Revision
132 0;
133
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 117 unchanged lines hidden (view full) ---

126 miscRegs[MISCREG_MIDR] =
127 (0x35 << 24) | //Implementor is '5' from "M5"
128 (0 << 20) | //Variant
129 (0xf << 16) | //Architecture from CPUID scheme
130 (0 << 4) | //Primary part number
131 (0 << 0) | //Revision
132 0;
133
134 // Separate Instruction and Data TLBs.
135 miscRegs[MISCREG_TLBTR] = 1;
136
134 //XXX We need to initialize the rest of the state.
135 }
136
137 MiscReg
138 readMiscRegNoEffect(int misc_reg)
139 {
140 assert(misc_reg < NumMiscRegs);
141 if (misc_reg == MISCREG_SPSR) {

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264 panic("Disabling coprocessors isn't implemented.\n");
265 }
266 newVal = newCpacr;
267 }
268 break;
269 case MISCREG_CSSELR:
270 warn("The csselr register isn't implemented.\n");
271 break;
137 //XXX We need to initialize the rest of the state.
138 }
139
140 MiscReg
141 readMiscRegNoEffect(int misc_reg)
142 {
143 assert(misc_reg < NumMiscRegs);
144 if (misc_reg == MISCREG_SPSR) {

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267 panic("Disabling coprocessors isn't implemented.\n");
268 }
269 newVal = newCpacr;
270 }
271 break;
272 case MISCREG_CSSELR:
273 warn("The csselr register isn't implemented.\n");
274 break;
275 case MISCREG_TLBTR:
276 return;
272 }
273 return setMiscRegNoEffect(misc_reg, newVal);
274 }
275
276 int
277 flattenIntIndex(int reg)
278 {
279 assert(reg >= 0);

--- 49 unchanged lines hidden --- 		277 }
278 return setMiscRegNoEffect(misc_reg, newVal);
279 }
280
281 int
282 flattenIntIndex(int reg)
283 {
284 assert(reg >= 0);

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