isa.hh (7348:c8103c298d68) isa.hh (7350:41e3ee23125e)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 105 unchanged lines hidden (view full) ---

114 // Enable CP 10, 11
115 cpacr.cp10 = 0x3;
116 cpacr.cp11 = 0x3;
117 miscRegs[MISCREG_CPACR] = cpacr;
118
119 /* One region, unified map. */
120 miscRegs[MISCREG_MPUIR] = 0x100;
121
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 105 unchanged lines hidden (view full) ---

114 // Enable CP 10, 11
115 cpacr.cp10 = 0x3;
116 cpacr.cp11 = 0x3;
117 miscRegs[MISCREG_CPACR] = cpacr;
118
119 /* One region, unified map. */
120 miscRegs[MISCREG_MPUIR] = 0x100;
121
122 /* Start with an event in the mailbox */
123 miscRegs[MISCREG_SEV_MAILBOX] = 1;
124
122 /*
123 * Implemented = '5' from "M5",
124 * Variant = 0,
125 */
126 miscRegs[MISCREG_MIDR] =
127 (0x35 << 24) | //Implementor is '5' from "M5"
128 (0 << 20) | //Variant
129 (0xf << 16) | //Architecture from CPUID scheme

--- 199 unchanged lines hidden --- 		125 /*
126 * Implemented = '5' from "M5",
127 * Variant = 0,
128 */
129 miscRegs[MISCREG_MIDR] =
130 (0x35 << 24) | //Implementor is '5' from "M5"
131 (0 << 20) | //Variant
132 (0xf << 16) | //Architecture from CPUID scheme

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