isa.hh (7320:6aacf11f7dbf) isa.hh (7348:c8103c298d68)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 224 unchanged lines hidden (view full) ---

233
234 void
235 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
236 {
237 MiscReg newVal = val;
238 if (misc_reg == MISCREG_CPSR) {
239 updateRegMap(val);
240 CPSR cpsr = val;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 224 unchanged lines hidden (view full) ---

233
234 void
235 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
236 {
237 MiscReg newVal = val;
238 if (misc_reg == MISCREG_CPSR) {
239 updateRegMap(val);
240 CPSR cpsr = val;
241 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
242 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
241 Addr npc = tc->readNextPC() & ~PcModeMask;
242 if (cpsr.j)
243 npc = npc | (ULL(1) << PcJBitShift);
244 if (cpsr.t)
245 npc = npc | (ULL(1) << PcTBitShift);
246
247 tc->setNextPC(npc);
248 }

--- 78 unchanged lines hidden --- 		243 Addr npc = tc->readNextPC() & ~PcModeMask;
244 if (cpsr.j)
245 npc = npc | (ULL(1) << PcJBitShift);
246 if (cpsr.t)
247 npc = npc | (ULL(1) << PcTBitShift);
248
249 tc->setNextPC(npc);
250 }

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