isa.hh (7310:239ab4e0c7d4) isa.hh (7320:6aacf11f7dbf)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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105 sctlr.rao3 = 1;
106 sctlr.rao4 = 1;
107 miscRegs[MISCREG_SCTLR] = sctlr;
108
109 /*
110 * Technically this should be 0, but we don't support those
111 * settings.
112 */
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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105 sctlr.rao3 = 1;
106 sctlr.rao4 = 1;
107 miscRegs[MISCREG_SCTLR] = sctlr;
108
109 /*
110 * Technically this should be 0, but we don't support those
111 * settings.
112 */
113 miscRegs[MISCREG_CPACR] = 0x0fffffff;
113 CPACR cpacr = 0;
114 // Enable CP 10, 11
115 cpacr.cp10 = 0x3;
116 cpacr.cp11 = 0x3;
117 miscRegs[MISCREG_CPACR] = cpacr;
114
115 /* One region, unified map. */
116 miscRegs[MISCREG_MPUIR] = 0x100;
117
118 /*
119 * Implemented = '5' from "M5",
120 * Variant = 0,
121 */

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244 }
245 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
246 misc_reg < MISCREG_CP15_END) {
247 panic("Unimplemented CP15 register %s wrote with %#x.\n",
248 miscRegName[misc_reg], val);
249 }
250 switch (misc_reg) {
251 case MISCREG_CPACR:
118
119 /* One region, unified map. */
120 miscRegs[MISCREG_MPUIR] = 0x100;
121
122 /*
123 * Implemented = '5' from "M5",
124 * Variant = 0,
125 */

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248 }
249 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
250 misc_reg < MISCREG_CP15_END) {
251 panic("Unimplemented CP15 register %s wrote with %#x.\n",
252 miscRegName[misc_reg], val);
253 }
254 switch (misc_reg) {
255 case MISCREG_CPACR:
252 newVal = bits(val, 27, 0);
253 if (newVal != 0x0fffffff) {
254 panic("Disabling coprocessors isn't implemented.\n");
256 {
257 CPACR newCpacr = 0;
258 CPACR valCpacr = val;
259 newCpacr.cp10 = valCpacr.cp10;
260 newCpacr.cp11 = valCpacr.cp11;
261 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
262 panic("Disabling coprocessors isn't implemented.\n");
263 }
264 newVal = newCpacr;
255 }
256 break;
257 case MISCREG_CSSELR:
258 warn("The csselr register isn't implemented.\n");
259 break;
260 }
261 return setMiscRegNoEffect(misc_reg, newVal);
262 }

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266 break;
267 case MISCREG_CSSELR:
268 warn("The csselr register isn't implemented.\n");
269 break;
270 }
271 return setMiscRegNoEffect(misc_reg, newVal);
272 }

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