isa.hh (7287:25c1718b819a) isa.hh (7298:1eb75247bdc6)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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107 miscRegs[MISCREG_SCTLR] = sctlr;
108
109 /*
110 * Technically this should be 0, but we don't support those
111 * settings.
112 */
113 miscRegs[MISCREG_CPACR] = 0x0fffffff;
114
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 98 unchanged lines hidden (view full) ---

107 miscRegs[MISCREG_SCTLR] = sctlr;
108
109 /*
110 * Technically this should be 0, but we don't support those
111 * settings.
112 */
113 miscRegs[MISCREG_CPACR] = 0x0fffffff;
114
115 /* One region, unified map. */
116 miscRegs[MISCREG_MPUIR] = 0x100;
117
118 /*
119 * Implemented = '5' from "M5",
120 * Variant = 0,
121 */
122 miscRegs[MISCREG_MIDR] =
123 (0x35 << 24) | //Implementor is '5' from "M5"
124 (0 << 20) | //Variant
125 (0xf << 16) | //Architecture from CPUID scheme
126 (0 << 4) | //Primary part number
127 (0 << 0) | //Revision
128 0;
129
115 //XXX We need to initialize the rest of the state.
116 }
117
118 MiscReg
119 readMiscRegNoEffect(int misc_reg)
120 {
121 assert(misc_reg < NumMiscRegs);
122 if (misc_reg == MISCREG_SPSR) {

--- 161 unchanged lines hidden --- 		130 //XXX We need to initialize the rest of the state.
131 }
132
133 MiscReg
134 readMiscRegNoEffect(int misc_reg)
135 {
136 assert(misc_reg < NumMiscRegs);
137 if (misc_reg == MISCREG_SPSR) {

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