isa.hh (7273:674fc83d1908) isa.hh (7287:25c1718b819a)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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163 misc_reg < MISCREG_CP15_END) {
164 panic("Unimplemented CP15 register %s read.\n",
165 miscRegName[misc_reg]);
166 }
167 switch (misc_reg) {
168 case MISCREG_CLIDR:
169 warn("The clidr register always reports 0 caches.\n");
170 break;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 154 unchanged lines hidden (view full) ---

163 misc_reg < MISCREG_CP15_END) {
164 panic("Unimplemented CP15 register %s read.\n",
165 miscRegName[misc_reg]);
166 }
167 switch (misc_reg) {
168 case MISCREG_CLIDR:
169 warn("The clidr register always reports 0 caches.\n");
170 break;
171 case MISCREG_CCSIDR:
172 warn("The ccsidr register isn't implemented and "
173 "always reads as 0.\n");
174 break;
171 }
172 return readMiscRegNoEffect(misc_reg);
173 }
174
175 void
176 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
177 {
178 assert(misc_reg < NumMiscRegs);

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230 }
231 switch (misc_reg) {
232 case MISCREG_CPACR:
233 newVal = bits(val, 27, 0);
234 if (newVal != 0x0fffffff) {
235 panic("Disabling coprocessors isn't implemented.\n");
236 }
237 break;
175 }
176 return readMiscRegNoEffect(misc_reg);
177 }
178
179 void
180 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
181 {
182 assert(misc_reg < NumMiscRegs);

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234 }
235 switch (misc_reg) {
236 case MISCREG_CPACR:
237 newVal = bits(val, 27, 0);
238 if (newVal != 0x0fffffff) {
239 panic("Disabling coprocessors isn't implemented.\n");
240 }
241 break;
242 case MISCREG_CSSELR:
243 warn("The csselr register isn't implemented.\n");
244 break;
238 }
239 return setMiscRegNoEffect(misc_reg, newVal);
240 }
241
242 int
243 flattenIntIndex(int reg)
244 {
245 assert(reg >= 0);

--- 31 unchanged lines hidden --- 		245 }
246 return setMiscRegNoEffect(misc_reg, newVal);
247 }
248
249 int
250 flattenIntIndex(int reg)
251 {
252 assert(reg >= 0);

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