isa.hh (7270:fab664da32cf) isa.hh (7271:c1f84426708a)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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101 SCTLR sctlr = 0;
102 sctlr.nmfi = 1;
103 sctlr.rao1 = 1;
104 sctlr.rao2 = 1;
105 sctlr.rao3 = 1;
106 sctlr.rao4 = 1;
107 miscRegs[MISCREG_SCTLR] = sctlr;
108
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 92 unchanged lines hidden (view full) ---

101 SCTLR sctlr = 0;
102 sctlr.nmfi = 1;
103 sctlr.rao1 = 1;
104 sctlr.rao2 = 1;
105 sctlr.rao3 = 1;
106 sctlr.rao4 = 1;
107 miscRegs[MISCREG_SCTLR] = sctlr;
108
109 /*
110 * Technically this should be 0, but we don't support those
111 * settings.
112 */
113 miscRegs[MISCREG_CPACR] = 0x0fffffff;
114
109 //XXX We need to initialize the rest of the state.
110 }
111
112 MiscReg
113 readMiscRegNoEffect(int misc_reg)
114 {
115 assert(misc_reg < NumMiscRegs);
116 if (misc_reg == MISCREG_SPSR) {

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195 }
196 }
197 miscRegs[misc_reg] = val;
198 }
199
200 void
201 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
202 {
115 //XXX We need to initialize the rest of the state.
116 }
117
118 MiscReg
119 readMiscRegNoEffect(int misc_reg)
120 {
121 assert(misc_reg < NumMiscRegs);
122 if (misc_reg == MISCREG_SPSR) {

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201 }
202 }
203 miscRegs[misc_reg] = val;
204 }
205
206 void
207 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
208 {
209 MiscReg newVal = val;
203 if (misc_reg == MISCREG_CPSR) {
204 updateRegMap(val);
205 CPSR cpsr = val;
206 Addr npc = tc->readNextPC() & ~PcModeMask;
207 if (cpsr.j)
208 npc = npc | (ULL(1) << PcJBitShift);
209 if (cpsr.t)
210 npc = npc | (ULL(1) << PcTBitShift);
211
212 tc->setNextPC(npc);
213 }
214 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
215 misc_reg < MISCREG_CP15_END) {
216 panic("Unimplemented CP15 register %s wrote with %#x.\n",
217 miscRegName[misc_reg], val);
218 }
210 if (misc_reg == MISCREG_CPSR) {
211 updateRegMap(val);
212 CPSR cpsr = val;
213 Addr npc = tc->readNextPC() & ~PcModeMask;
214 if (cpsr.j)
215 npc = npc | (ULL(1) << PcJBitShift);
216 if (cpsr.t)
217 npc = npc | (ULL(1) << PcTBitShift);
218
219 tc->setNextPC(npc);
220 }
221 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
222 misc_reg < MISCREG_CP15_END) {
223 panic("Unimplemented CP15 register %s wrote with %#x.\n",
224 miscRegName[misc_reg], val);
225 }
219 return setMiscRegNoEffect(misc_reg, val);
226 switch (misc_reg) {
227 case MISCREG_CPACR:
228 newVal = bits(val, 27, 0);
229 if (newVal != 0x0fffffff) {
230 panic("Disabling coprocessors isn't implemented.\n");
231 }
232 break;
233 }
234 return setMiscRegNoEffect(misc_reg, newVal);
220 }
221
222 int
223 flattenIntIndex(int reg)
224 {
225 assert(reg >= 0);
226 if (reg < NUM_ARCH_INTREGS) {
227 return intRegMap[reg];

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236
237 int
238 flattenIntIndex(int reg)
239 {
240 assert(reg >= 0);
241 if (reg < NUM_ARCH_INTREGS) {
242 return intRegMap[reg];

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