isa.hh (7093:9832d4b070fc) isa.hh (7259:200840489735)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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147 else
148 cpsr.j = 0;
149 if (pc & (ULL(1) << PcTBitShift))
150 cpsr.t = 1;
151 else
152 cpsr.t = 0;
153 return cpsr;
154 }
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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147 else
148 cpsr.j = 0;
149 if (pc & (ULL(1) << PcTBitShift))
150 cpsr.t = 1;
151 else
152 cpsr.t = 0;
153 return cpsr;
154 }
155 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
156 misc_reg < MISCREG_CP15_END) {
157 panic("Unimplemented CP15 register %s read.\n",
158 miscRegName[misc_reg]);
159 }
155 return readMiscRegNoEffect(misc_reg);
156 }
157
158 void
159 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
160 {
161 assert(misc_reg < NumMiscRegs);
162 if (misc_reg == MISCREG_SPSR) {

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200 Addr npc = tc->readNextPC() & ~PcModeMask;
201 if (cpsr.j)
202 npc = npc | (ULL(1) << PcJBitShift);
203 if (cpsr.t)
204 npc = npc | (ULL(1) << PcTBitShift);
205
206 tc->setNextPC(npc);
207 }
160 return readMiscRegNoEffect(misc_reg);
161 }
162
163 void
164 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
165 {
166 assert(misc_reg < NumMiscRegs);
167 if (misc_reg == MISCREG_SPSR) {

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205 Addr npc = tc->readNextPC() & ~PcModeMask;
206 if (cpsr.j)
207 npc = npc | (ULL(1) << PcJBitShift);
208 if (cpsr.t)
209 npc = npc | (ULL(1) << PcTBitShift);
210
211 tc->setNextPC(npc);
212 }
213 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
214 misc_reg < MISCREG_CP15_END) {
215 panic("Unimplemented CP15 register %s wrote with %#x.\n",
216 miscRegName[misc_reg], val);
217 }
208 return setMiscRegNoEffect(misc_reg, val);
209 }
210
211 int
212 flattenIntIndex(int reg)
213 {
214 assert(reg >= 0);
215 if (reg < NUM_ARCH_INTREGS) {

--- 30 unchanged lines hidden --- 		218 return setMiscRegNoEffect(misc_reg, val);
219 }
220
221 int
222 flattenIntIndex(int reg)
223 {
224 assert(reg >= 0);
225 if (reg < NUM_ARCH_INTREGS) {

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