isa.hh (6735:6437ad24a8a0) isa.hh (6745:cdc62b81747e)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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95
96 //XXX We need to initialize the rest of the state.
97 }
98
99 MiscReg
100 readMiscRegNoEffect(int misc_reg)
101 {
102 assert(misc_reg < NumMiscRegs);
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 86 unchanged lines hidden (view full) ---

95
96 //XXX We need to initialize the rest of the state.
97 }
98
99 MiscReg
100 readMiscRegNoEffect(int misc_reg)
101 {
102 assert(misc_reg < NumMiscRegs);
103 if (misc_reg == MISCREG_SPSR) {
104 CPSR cpsr = miscRegs[MISCREG_CPSR];
105 switch (cpsr.mode) {
106 case MODE_USER:
107 return miscRegs[MISCREG_SPSR];
108 case MODE_FIQ:
109 return miscRegs[MISCREG_SPSR_FIQ];
110 case MODE_IRQ:
111 return miscRegs[MISCREG_SPSR_IRQ];
112 case MODE_SVC:
113 return miscRegs[MISCREG_SPSR_SVC];
114 case MODE_MON:
115 return miscRegs[MISCREG_SPSR_MON];
116 case MODE_ABORT:
117 return miscRegs[MISCREG_SPSR_ABT];
118 case MODE_UNDEFINED:
119 return miscRegs[MISCREG_SPSR_UND];
120 default:
121 return miscRegs[MISCREG_SPSR];
122 }
123 }
103 return miscRegs[misc_reg];
104 }
105
106 MiscReg
107 readMiscReg(int misc_reg, ThreadContext *tc)
108 {
124 return miscRegs[misc_reg];
125 }
126
127 MiscReg
128 readMiscReg(int misc_reg, ThreadContext *tc)
129 {
109 assert(misc_reg < NumMiscRegs);
110 return miscRegs[misc_reg];
130 return readMiscRegNoEffect(misc_reg);
111 }
112
113 void
114 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
115 {
116 assert(misc_reg < NumMiscRegs);
131 }
132
133 void
134 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
135 {
136 assert(misc_reg < NumMiscRegs);
137 if (misc_reg == MISCREG_SPSR) {
138 CPSR cpsr = miscRegs[MISCREG_CPSR];
139 switch (cpsr.mode) {
140 case MODE_USER:
141 miscRegs[MISCREG_SPSR] = val;
142 return;
143 case MODE_FIQ:
144 miscRegs[MISCREG_SPSR_FIQ] = val;
145 return;
146 case MODE_IRQ:
147 miscRegs[MISCREG_SPSR_IRQ] = val;
148 return;
149 case MODE_SVC:
150 miscRegs[MISCREG_SPSR_SVC] = val;
151 return;
152 case MODE_MON:
153 miscRegs[MISCREG_SPSR_MON] = val;
154 return;
155 case MODE_ABORT:
156 miscRegs[MISCREG_SPSR_ABT] = val;
157 return;
158 case MODE_UNDEFINED:
159 miscRegs[MISCREG_SPSR_UND] = val;
160 return;
161 default:
162 miscRegs[MISCREG_SPSR] = val;
163 return;
164 }
165 }
117 miscRegs[misc_reg] = val;
118 }
119
120 void
121 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
122 {
123 if (misc_reg == MISCREG_CPSR) {
124 updateRegMap(val);
125 }
166 miscRegs[misc_reg] = val;
167 }
168
169 void
170 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
171 {
172 if (misc_reg == MISCREG_CPSR) {
173 updateRegMap(val);
174 }
126 assert(misc_reg < NumMiscRegs);
127 miscRegs[misc_reg] = val;
175 return setMiscRegNoEffect(misc_reg, val);
128 }
129
130 int
131 flattenIntIndex(int reg)
132 {
133 assert(reg >= 0);
134 if (reg < NUM_ARCH_INTREGS) {
135 return intRegMap[reg];

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177
178 int
179 flattenIntIndex(int reg)
180 {
181 assert(reg >= 0);
182 if (reg < NUM_ARCH_INTREGS) {
183 return intRegMap[reg];

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