isa.hh (14000:d85c61dc0b5c) isa.hh (14128:6ed23d07d0d1)
1/*
1/*
2 * Copyright (c) 2010, 2012-2018 ARM Limited
2 * Copyright (c) 2010, 2012-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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90 bool haveSecurity;
91 bool haveLPAE;
92 bool haveVirtualization;
93 bool haveCrypto;
94 bool haveLargeAsid64;
95 bool haveGICv3CPUInterface;
96 uint8_t physAddrRange;
97 bool haveSVE;
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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90 bool haveSecurity;
91 bool haveLPAE;
92 bool haveVirtualization;
93 bool haveCrypto;
94 bool haveLargeAsid64;
95 bool haveGICv3CPUInterface;
96 uint8_t physAddrRange;
97 bool haveSVE;
98 bool havePAN;
98
99 /** SVE vector length in quadwords */
100 unsigned sveVL;
101
102 /**
103 * If true, accesses to IMPLEMENTATION DEFINED registers are treated
104 * as NOP hence not causing UNDEFINED INSTRUCTION.
105 */

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681 SERIALIZE_SCALAR(highestELIs64);
682 SERIALIZE_SCALAR(haveSecurity);
683 SERIALIZE_SCALAR(haveLPAE);
684 SERIALIZE_SCALAR(haveVirtualization);
685 SERIALIZE_SCALAR(haveLargeAsid64);
686 SERIALIZE_SCALAR(physAddrRange);
687 SERIALIZE_SCALAR(haveSVE);
688 SERIALIZE_SCALAR(sveVL);
99
100 /** SVE vector length in quadwords */
101 unsigned sveVL;
102
103 /**
104 * If true, accesses to IMPLEMENTATION DEFINED registers are treated
105 * as NOP hence not causing UNDEFINED INSTRUCTION.
106 */

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682 SERIALIZE_SCALAR(highestELIs64);
683 SERIALIZE_SCALAR(haveSecurity);
684 SERIALIZE_SCALAR(haveLPAE);
685 SERIALIZE_SCALAR(haveVirtualization);
686 SERIALIZE_SCALAR(haveLargeAsid64);
687 SERIALIZE_SCALAR(physAddrRange);
688 SERIALIZE_SCALAR(haveSVE);
689 SERIALIZE_SCALAR(sveVL);
690 SERIALIZE_SCALAR(havePAN);
689 }
690 void unserialize(CheckpointIn &cp)
691 {
692 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
693 UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
694 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
695 updateRegMap(tmp_cpsr);
696
697 UNSERIALIZE_SCALAR(highestELIs64);
698 UNSERIALIZE_SCALAR(haveSecurity);
699 UNSERIALIZE_SCALAR(haveLPAE);
700 UNSERIALIZE_SCALAR(haveVirtualization);
701 UNSERIALIZE_SCALAR(haveLargeAsid64);
702 UNSERIALIZE_SCALAR(physAddrRange);
703 UNSERIALIZE_SCALAR(haveSVE);
704 UNSERIALIZE_SCALAR(sveVL);
691 }
692 void unserialize(CheckpointIn &cp)
693 {
694 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
695 UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
696 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
697 updateRegMap(tmp_cpsr);
698
699 UNSERIALIZE_SCALAR(highestELIs64);
700 UNSERIALIZE_SCALAR(haveSecurity);
701 UNSERIALIZE_SCALAR(haveLPAE);
702 UNSERIALIZE_SCALAR(haveVirtualization);
703 UNSERIALIZE_SCALAR(haveLargeAsid64);
704 UNSERIALIZE_SCALAR(physAddrRange);
705 UNSERIALIZE_SCALAR(haveSVE);
706 UNSERIALIZE_SCALAR(sveVL);
707 UNSERIALIZE_SCALAR(havePAN);
705 }
706
707 void startup(ThreadContext *tc);
708
709 Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
710
711 /** Getter for haveGICv3CPUInterface */
712 bool haveGICv3CpuIfc() const

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709
710 void startup(ThreadContext *tc);
711
712 Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
713
714 /** Getter for haveGICv3CPUInterface */
715 bool haveGICv3CpuIfc() const

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