isa.hh (13759:9941fca869a9) isa.hh (14000:d85c61dc0b5c)
1/*
2 * Copyright (c) 2010, 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 91 unchanged lines hidden (view full) ---

100 unsigned sveVL;
101
102 /**
103 * If true, accesses to IMPLEMENTATION DEFINED registers are treated
104 * as NOP hence not causing UNDEFINED INSTRUCTION.
105 */
106 bool impdefAsNop;
107
1/*
2 * Copyright (c) 2010, 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 91 unchanged lines hidden (view full) ---

100 unsigned sveVL;
101
102 /**
103 * If true, accesses to IMPLEMENTATION DEFINED registers are treated
104 * as NOP hence not causing UNDEFINED INSTRUCTION.
105 */
106 bool impdefAsNop;
107
108 bool afterStartup;
109
108 /** MiscReg metadata **/
109 struct MiscRegLUTEntry {
110 uint32_t lower; // Lower half mapped to this register
111 uint32_t upper; // Upper half mapped to this register
112 uint64_t _reset; // value taken on reset (i.e. initialization)
113 uint64_t _res0; // reserved
114 uint64_t _res1; // reserved
115 uint64_t _raz; // read as zero (fixed at 0)

--- 585 unchanged lines hidden (view full) ---

701 UNSERIALIZE_SCALAR(haveSVE);
702 UNSERIALIZE_SCALAR(sveVL);
703 }
704
705 void startup(ThreadContext *tc);
706
707 Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
708
110 /** MiscReg metadata **/
111 struct MiscRegLUTEntry {
112 uint32_t lower; // Lower half mapped to this register
113 uint32_t upper; // Upper half mapped to this register
114 uint64_t _reset; // value taken on reset (i.e. initialization)
115 uint64_t _res0; // reserved
116 uint64_t _res1; // reserved
117 uint64_t _raz; // read as zero (fixed at 0)

--- 585 unchanged lines hidden (view full) ---

703 UNSERIALIZE_SCALAR(haveSVE);
704 UNSERIALIZE_SCALAR(sveVL);
705 }
706
707 void startup(ThreadContext *tc);
708
709 Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
710
711 /** Getter for haveGICv3CPUInterface */
712 bool haveGICv3CpuIfc() const
713 {
714 // haveGICv3CPUInterface is initialized at startup time, hence
715 // trying to read its value before the startup stage will lead
716 // to an error
717 assert(afterStartup);
718 return haveGICv3CPUInterface;
719 }
720
709 Enums::VecRegRenameMode
710 vecRegRenameMode() const
711 {
712 return _vecRegRenameMode;
713 }
714
715 /// Explicitly import the otherwise hidden startup
716 using SimObject::startup;

--- 36 unchanged lines hidden ---
721 Enums::VecRegRenameMode
722 vecRegRenameMode() const
723 {
724 return _vecRegRenameMode;
725 }
726
727 /// Explicitly import the otherwise hidden startup
728 using SimObject::startup;

--- 36 unchanged lines hidden ---