isa.hh (13601:f5c84915eb7f) isa.hh (13610:5d5404ac6288)
1/*
2 * Copyright (c) 2010, 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 432 unchanged lines hidden (view full) ---

441 return RegId(IntRegClass, flattenIntIndex(regId.index()));
442 case FloatRegClass:
443 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
444 case VecRegClass:
445 return RegId(VecRegClass, flattenVecIndex(regId.index()));
446 case VecElemClass:
447 return RegId(VecElemClass, flattenVecElemIndex(regId.index()),
448 regId.elemIndex());
1/*
2 * Copyright (c) 2010, 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 432 unchanged lines hidden (view full) ---

441 return RegId(IntRegClass, flattenIntIndex(regId.index()));
442 case FloatRegClass:
443 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
444 case VecRegClass:
445 return RegId(VecRegClass, flattenVecIndex(regId.index()));
446 case VecElemClass:
447 return RegId(VecElemClass, flattenVecElemIndex(regId.index()),
448 regId.elemIndex());
449 case VecPredRegClass:
450 return RegId(VecPredRegClass,
451 flattenVecPredIndex(regId.index()));
449 case CCRegClass:
450 return RegId(CCRegClass, flattenCCIndex(regId.index()));
451 case MiscRegClass:
452 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
453 }
454 return RegId();
455 }
456

--- 46 unchanged lines hidden (view full) ---

503 int
504 flattenVecElemIndex(int reg) const
505 {
506 assert(reg >= 0);
507 return reg;
508 }
509
510 int
452 case CCRegClass:
453 return RegId(CCRegClass, flattenCCIndex(regId.index()));
454 case MiscRegClass:
455 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
456 }
457 return RegId();
458 }
459

--- 46 unchanged lines hidden (view full) ---

506 int
507 flattenVecElemIndex(int reg) const
508 {
509 assert(reg >= 0);
510 return reg;
511 }
512
513 int
514 flattenVecPredIndex(int reg) const
515 {
516 assert(reg >= 0);
517 return reg;
518 }
519
520 int
511 flattenCCIndex(int reg) const
512 {
513 assert(reg >= 0);
514 return reg;
515 }
516
517 int
518 flattenMiscIndex(int reg) const

--- 209 unchanged lines hidden --- 		521 flattenCCIndex(int reg) const
522 {
523 assert(reg >= 0);
524 return reg;
525 }
526
527 int
528 flattenMiscIndex(int reg) const

--- 209 unchanged lines hidden ---