isa.hh (13545:dd7ca2be0f2b) isa.hh (13581:b6dcd0183747)
1/*
2 * Copyright (c) 2010, 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 348 unchanged lines hidden (view full) ---

357
358 const MiscRegLUTEntryInitializer InitReg(uint32_t reg) {
359 return MiscRegLUTEntryInitializer(lookUpMiscReg[reg],
360 miscRegInfo[reg]);
361 }
362
363 void initializeMiscRegMetadata();
364
1/*
2 * Copyright (c) 2010, 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 348 unchanged lines hidden (view full) ---

357
358 const MiscRegLUTEntryInitializer InitReg(uint32_t reg) {
359 return MiscRegLUTEntryInitializer(lookUpMiscReg[reg],
360 miscRegInfo[reg]);
361 }
362
363 void initializeMiscRegMetadata();
364
365 MiscReg miscRegs[NumMiscRegs];
365 RegVal miscRegs[NumMiscRegs];
366 const IntRegIndex *intRegMap;
367
368 void
369 updateRegMap(CPSR cpsr)
370 {
371 if (cpsr.width == 0) {
372 intRegMap = IntReg64Map;
373 } else {

--- 49 unchanged lines hidden (view full) ---

423
424 protected:
425 void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
426 void clear64(const ArmISAParams *p);
427 void initID32(const ArmISAParams *p);
428 void initID64(const ArmISAParams *p);
429
430 public:
366 const IntRegIndex *intRegMap;
367
368 void
369 updateRegMap(CPSR cpsr)
370 {
371 if (cpsr.width == 0) {
372 intRegMap = IntReg64Map;
373 } else {

--- 49 unchanged lines hidden (view full) ---

423
424 protected:
425 void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
426 void clear64(const ArmISAParams *p);
427 void initID32(const ArmISAParams *p);
428 void initID64(const ArmISAParams *p);
429
430 public:
431 MiscReg readMiscRegNoEffect(int misc_reg) const;
432 MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
433 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
434 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
431 RegVal readMiscRegNoEffect(int misc_reg) const;
432 RegVal readMiscReg(int misc_reg, ThreadContext *tc);
433 void setMiscRegNoEffect(int misc_reg, const RegVal &val);
434 void setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc);
435
436 RegId
437 flattenRegId(const RegId& regId) const
438 {
439 switch (regId.classValue()) {
440 case IntRegClass:
441 return RegId(IntRegClass, flattenIntIndex(regId.index()));
442 case FloatRegClass:

--- 272 unchanged lines hidden --- 		435
436 RegId
437 flattenRegId(const RegId& regId) const
438 {
439 switch (regId.classValue()) {
440 case IntRegClass:
441 return RegId(IntRegClass, flattenIntIndex(regId.index()));
442 case FloatRegClass:

--- 272 unchanged lines hidden ---