isa.hh (13395:0f064dae9f6b) isa.hh (13531:e6f1bf55d038)
1/*
2 * Copyright (c) 2010, 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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77 DummyISADevice dummyDevice;
78
79 // PMU belonging to this ISA
80 BaseISADevice *pmu;
81
82 // Generic timer interface belonging to this ISA
83 std::unique_ptr<BaseISADevice> timer;
84
1/*
2 * Copyright (c) 2010, 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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77 DummyISADevice dummyDevice;
78
79 // PMU belonging to this ISA
80 BaseISADevice *pmu;
81
82 // Generic timer interface belonging to this ISA
83 std::unique_ptr<BaseISADevice> timer;
84
85 // GICv3 CPU interface belonging to this ISA
86 std::unique_ptr<BaseISADevice> gicv3CpuInterface;
87
85 // Cached copies of system-level properties
86 bool highestELIs64;
87 bool haveSecurity;
88 bool haveLPAE;
89 bool haveVirtualization;
90 bool haveCrypto;
91 bool haveLargeAsid64;
88 // Cached copies of system-level properties
89 bool highestELIs64;
90 bool haveSecurity;
91 bool haveLPAE;
92 bool haveVirtualization;
93 bool haveCrypto;
94 bool haveLargeAsid64;
95 bool haveGICv3CPUInterface;
92 uint8_t physAddrRange;
93
94 /**
95 * If true, accesses to IMPLEMENTATION DEFINED registers are treated
96 * as NOP hence not causing UNDEFINED INSTRUCTION.
97 */
98 bool impdefAsNop;
99

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395 break;
396 default:
397 panic("Unrecognized mode setting in CPSR.\n");
398 }
399 }
400 }
401
402 BaseISADevice &getGenericTimer(ThreadContext *tc);
96 uint8_t physAddrRange;
97
98 /**
99 * If true, accesses to IMPLEMENTATION DEFINED registers are treated
100 * as NOP hence not causing UNDEFINED INSTRUCTION.
101 */
102 bool impdefAsNop;
103

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399 break;
400 default:
401 panic("Unrecognized mode setting in CPSR.\n");
402 }
403 }
404 }
405
406 BaseISADevice &getGenericTimer(ThreadContext *tc);
407 BaseISADevice &getGICv3CPUInterface(ThreadContext *tc);
403
404
405 private:
406 inline void assert32(ThreadContext *tc) {
407 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
408 assert(cpsr.width);
409 }
410

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409
410 private:
411 inline void assert32(ThreadContext *tc) {
412 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
413 assert(cpsr.width);
414 }
415

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