isa.hh (12477:3d6c49bc7290) isa.hh (12478:604310e2d7ad)
1/*
2 * Copyright (c) 2010, 2012-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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84 // Cached copies of system-level properties
85 bool highestELIs64;
86 bool haveSecurity;
87 bool haveLPAE;
88 bool haveVirtualization;
89 bool haveLargeAsid64;
90 uint8_t physAddrRange64;
91
1/*
2 * Copyright (c) 2010, 2012-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 75 unchanged lines hidden (view full) ---

84 // Cached copies of system-level properties
85 bool highestELIs64;
86 bool haveSecurity;
87 bool haveLPAE;
88 bool haveVirtualization;
89 bool haveLargeAsid64;
90 uint8_t physAddrRange64;
91
92 /** Register translation entry used in lookUpMiscReg */
92 /** MiscReg metadata **/
93 struct MiscRegLUTEntry {
94 uint32_t lower; // Lower half mapped to this register
95 uint32_t upper; // Upper half mapped to this register
93 struct MiscRegLUTEntry {
94 uint32_t lower; // Lower half mapped to this register
95 uint32_t upper; // Upper half mapped to this register
96 uint64_t _reset; // value taken on reset (i.e. initialization)
97 uint64_t _res0; // reserved
98 uint64_t _res1; // reserved
99 uint64_t _raz; // read as zero (fixed at 0)
100 uint64_t _rao; // read as one (fixed at 1)
101 public:
102 MiscRegLUTEntry() :
103 lower(0), upper(0),
104 _reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {}
105 uint64_t reset() const { return _reset; }
106 uint64_t res0() const { return _res0; }
107 uint64_t res1() const { return _res1; }
108 uint64_t raz() const { return _raz; }
109 uint64_t rao() const { return _rao; }
110 // raz/rao implies writes ignored
111 uint64_t wi() const { return _raz | _rao; }
96 };
97
98 /** Metadata table accessible via the value of the register */
99 std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
100
101 class MiscRegLUTEntryInitializer {
102 struct MiscRegLUTEntry &entry;
103 typedef const MiscRegLUTEntryInitializer& chain;
104 public:
105 chain mapsTo(uint32_t l, uint32_t u = 0) const {
106 entry.lower = l;
107 entry.upper = u;
108 return *this;
109 }
112 };
113
114 /** Metadata table accessible via the value of the register */
115 std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
116
117 class MiscRegLUTEntryInitializer {
118 struct MiscRegLUTEntry &entry;
119 typedef const MiscRegLUTEntryInitializer& chain;
120 public:
121 chain mapsTo(uint32_t l, uint32_t u = 0) const {
122 entry.lower = l;
123 entry.upper = u;
124 return *this;
125 }
126 chain res0(uint64_t mask) const {
127 entry._res0 = mask;
128 return *this;
129 }
130 chain res1(uint64_t mask) const {
131 entry._res1 = mask;
132 return *this;
133 }
134 chain raz(uint64_t mask) const {
135 entry._raz = mask;
136 return *this;
137 }
138 chain rao(uint64_t mask) const {
139 entry._rao = mask;
140 return *this;
141 }
110 MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e)
111 : entry(e)
112 {}
113 };
114
115 const MiscRegLUTEntryInitializer InitReg(uint32_t reg) {
116 return MiscRegLUTEntryInitializer(lookUpMiscReg[reg]);
117 }

--- 355 unchanged lines hidden --- 		142 MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e)
143 : entry(e)
144 {}
145 };
146
147 const MiscRegLUTEntryInitializer InitReg(uint32_t reg) {
148 return MiscRegLUTEntryInitializer(lookUpMiscReg[reg]);
149 }

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