isa.hh (11768:5b80960dcf08) isa.hh (11771:764eae95bbbb)
1/*
2 * Copyright (c) 2010, 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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74
75 // PMU belonging to this ISA
76 BaseISADevice *pmu;
77
78 // Generic timer interface belonging to this ISA
79 std::unique_ptr<BaseISADevice> timer;
80
81 // Cached copies of system-level properties
1/*
2 * Copyright (c) 2010, 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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74
75 // PMU belonging to this ISA
76 BaseISADevice *pmu;
77
78 // Generic timer interface belonging to this ISA
79 std::unique_ptr<BaseISADevice> timer;
80
81 // Cached copies of system-level properties
82 bool highestELIs64;
82 bool haveSecurity;
83 bool haveLPAE;
84 bool haveVirtualization;
85 bool haveLargeAsid64;
86 uint8_t physAddrRange64;
87
88 /** Register translation entry used in lookUpMiscReg */
89 struct MiscRegLUTEntry {

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323 }
324 break;
325 default:
326 panic("Unrecognized misc. register.\n");
327 break;
328 }
329 } else {
330 if (miscRegInfo[reg][MISCREG_BANKED]) {
83 bool haveSecurity;
84 bool haveLPAE;
85 bool haveVirtualization;
86 bool haveLargeAsid64;
87 uint8_t physAddrRange64;
88
89 /** Register translation entry used in lookUpMiscReg */
90 struct MiscRegLUTEntry {

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324 }
325 break;
326 default:
327 panic("Unrecognized misc. register.\n");
328 break;
329 }
330 } else {
331 if (miscRegInfo[reg][MISCREG_BANKED]) {
331 bool secureReg = haveSecurity &&
332 bool secureReg = haveSecurity && !highestELIs64 &&
332 inSecureState(miscRegs[MISCREG_SCR],
333 miscRegs[MISCREG_CPSR]);
334 flat_idx += secureReg ? 2 : 1;
335 }
336 }
337 return flat_idx;
338 }
339
333 inSecureState(miscRegs[MISCREG_SCR],
334 miscRegs[MISCREG_CPSR]);
335 flat_idx += secureReg ? 2 : 1;
336 }
337 }
338 return flat_idx;
339 }
340
341 std::pair<int,int> getMiscIndices(int misc_reg) const
342 {
343 // Note: indexes of AArch64 registers are left unchanged
344 int flat_idx = flattenMiscIndex(misc_reg);
345
346 if (lookUpMiscReg[flat_idx].lower == 0) {
347 return std::make_pair(flat_idx, 0);
348 }
349
350 // do additional S/NS flattenings if mapped to NS while in S
351 bool S = haveSecurity && !highestELIs64 &&
352 inSecureState(miscRegs[MISCREG_SCR],
353 miscRegs[MISCREG_CPSR]);
354 int lower = lookUpMiscReg[flat_idx].lower;
355 int upper = lookUpMiscReg[flat_idx].upper;
356 // upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
357 lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD];
358 upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD];
359 return std::make_pair(lower, upper);
360 }
361
340 void serialize(CheckpointOut &cp) const
341 {
342 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
343 SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
344
362 void serialize(CheckpointOut &cp) const
363 {
364 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
365 SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
366
367 SERIALIZE_SCALAR(highestELIs64);
345 SERIALIZE_SCALAR(haveSecurity);
346 SERIALIZE_SCALAR(haveLPAE);
347 SERIALIZE_SCALAR(haveVirtualization);
348 SERIALIZE_SCALAR(haveLargeAsid64);
349 SERIALIZE_SCALAR(physAddrRange64);
350 }
351 void unserialize(CheckpointIn &cp)
352 {
353 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
354 UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
355 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
356 updateRegMap(tmp_cpsr);
357
368 SERIALIZE_SCALAR(haveSecurity);
369 SERIALIZE_SCALAR(haveLPAE);
370 SERIALIZE_SCALAR(haveVirtualization);
371 SERIALIZE_SCALAR(haveLargeAsid64);
372 SERIALIZE_SCALAR(physAddrRange64);
373 }
374 void unserialize(CheckpointIn &cp)
375 {
376 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
377 UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
378 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
379 updateRegMap(tmp_cpsr);
380
381 UNSERIALIZE_SCALAR(highestELIs64);
358 UNSERIALIZE_SCALAR(haveSecurity);
359 UNSERIALIZE_SCALAR(haveLPAE);
360 UNSERIALIZE_SCALAR(haveVirtualization);
361 UNSERIALIZE_SCALAR(haveLargeAsid64);
362 UNSERIALIZE_SCALAR(physAddrRange64);
363 }
364
365 void startup(ThreadContext *tc) {}

--- 15 unchanged lines hidden --- 		382 UNSERIALIZE_SCALAR(haveSecurity);
383 UNSERIALIZE_SCALAR(haveLPAE);
384 UNSERIALIZE_SCALAR(haveVirtualization);
385 UNSERIALIZE_SCALAR(haveLargeAsid64);
386 UNSERIALIZE_SCALAR(physAddrRange64);
387 }
388
389 void startup(ThreadContext *tc) {}

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