isa.hh (11574:868c31fcca24) isa.hh (11768:5b80960dcf08)
1/*
2 * Copyright (c) 2010, 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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55struct ArmISAParams;
56struct DummyArmISADeviceParams;
57class ThreadContext;
58class Checkpoint;
59class EventManager;
60
61namespace ArmISA
62{
1/*
2 * Copyright (c) 2010, 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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55struct ArmISAParams;
56struct DummyArmISADeviceParams;
57class ThreadContext;
58class Checkpoint;
59class EventManager;
60
61namespace ArmISA
62{
63
64 /**
65 * At the moment there are 57 registers which need to be aliased/
66 * translated with other registers in the ISA. This enum helps with that
67 * translation.
68 */
69 enum translateTable {
70 miscRegTranslateCSSELR_EL1,
71 miscRegTranslateSCTLR_EL1,
72 miscRegTranslateSCTLR_EL2,
73 miscRegTranslateACTLR_EL1,
74 miscRegTranslateACTLR_EL2,
75 miscRegTranslateCPACR_EL1,
76 miscRegTranslateCPTR_EL2,
77 miscRegTranslateHCR_EL2,
78 miscRegTranslateMDCR_EL2,
79 miscRegTranslateHSTR_EL2,
80 miscRegTranslateHACR_EL2,
81 miscRegTranslateTTBR0_EL1,
82 miscRegTranslateTTBR1_EL1,
83 miscRegTranslateTTBR0_EL2,
84 miscRegTranslateVTTBR_EL2,
85 miscRegTranslateTCR_EL1,
86 miscRegTranslateTCR_EL2,
87 miscRegTranslateVTCR_EL2,
88 miscRegTranslateAFSR0_EL1,
89 miscRegTranslateAFSR1_EL1,
90 miscRegTranslateAFSR0_EL2,
91 miscRegTranslateAFSR1_EL2,
92 miscRegTranslateESR_EL2,
93 miscRegTranslateFAR_EL1,
94 miscRegTranslateFAR_EL2,
95 miscRegTranslateHPFAR_EL2,
96 miscRegTranslatePAR_EL1,
97 miscRegTranslateMAIR_EL1,
98 miscRegTranslateMAIR_EL2,
99 miscRegTranslateAMAIR_EL1,
100 miscRegTranslateVBAR_EL1,
101 miscRegTranslateVBAR_EL2,
102 miscRegTranslateCONTEXTIDR_EL1,
103 miscRegTranslateTPIDR_EL0,
104 miscRegTranslateTPIDRRO_EL0,
105 miscRegTranslateTPIDR_EL1,
106 miscRegTranslateTPIDR_EL2,
107 miscRegTranslateTEECR32_EL1,
108 miscRegTranslateCNTFRQ_EL0,
109 miscRegTranslateCNTPCT_EL0,
110 miscRegTranslateCNTVCT_EL0,
111 miscRegTranslateCNTVOFF_EL2,
112 miscRegTranslateCNTKCTL_EL1,
113 miscRegTranslateCNTHCTL_EL2,
114 miscRegTranslateCNTP_TVAL_EL0,
115 miscRegTranslateCNTP_CTL_EL0,
116 miscRegTranslateCNTP_CVAL_EL0,
117 miscRegTranslateCNTV_TVAL_EL0,
118 miscRegTranslateCNTV_CTL_EL0,
119 miscRegTranslateCNTV_CVAL_EL0,
120 miscRegTranslateCNTHP_TVAL_EL2,
121 miscRegTranslateCNTHP_CTL_EL2,
122 miscRegTranslateCNTHP_CVAL_EL2,
123 miscRegTranslateDACR32_EL2,
124 miscRegTranslateIFSR32_EL2,
125 miscRegTranslateTEEHBR32_EL1,
126 miscRegTranslateSDER32_EL3,
127 miscRegTranslateMax
128 };
129
130 class ISA : public SimObject
131 {
132 protected:
133 // Parent system
134 ArmSystem *system;
135
136 // Micro Architecture
137 const Enums::DecoderFlavour _decoderFlavour;

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159 };
160
161 struct MiscRegInitializerEntry {
162 uint32_t index;
163 struct MiscRegLUTEntry entry;
164 };
165
166 /** Register table noting all translations */
63 class ISA : public SimObject
64 {
65 protected:
66 // Parent system
67 ArmSystem *system;
68
69 // Micro Architecture
70 const Enums::DecoderFlavour _decoderFlavour;

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92 };
93
94 struct MiscRegInitializerEntry {
95 uint32_t index;
96 struct MiscRegLUTEntry entry;
97 };
98
99 /** Register table noting all translations */
167 static const struct MiscRegInitializerEntry
168 MiscRegSwitch[miscRegTranslateMax];
100 static const struct MiscRegInitializerEntry MiscRegSwitch[];
169
170 /** Translation table accessible via the value of the register */
171 std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
172
173 MiscReg miscRegs[NumMiscRegs];
174 const IntRegIndex *intRegMap;
175
176 void

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102 /** Translation table accessible via the value of the register */
103 std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
104
105 MiscReg miscRegs[NumMiscRegs];
106 const IntRegIndex *intRegMap;
107
108 void

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