isa.hh (10934:5af8f40d8f2c) isa.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2010, 2012-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 274 unchanged lines hidden (view full) ---

283 int
284 flattenCCIndex(int reg) const
285 {
286 assert(reg >= 0);
287 return reg;
288 }
289
290 int
1/*
2 * Copyright (c) 2010, 2012-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 274 unchanged lines hidden (view full) ---

283 int
284 flattenCCIndex(int reg) const
285 {
286 assert(reg >= 0);
287 return reg;
288 }
289
290 int
291 flattenVectorIndex(int reg) const
292 {
293 assert(reg >= 0);
294 return reg;
295 }
296
297 int
298 flattenMiscIndex(int reg) const
299 {
300 assert(reg >= 0);
301 int flat_idx = reg;
302
303 if (reg == MISCREG_SPSR) {
304 CPSR cpsr = miscRegs[MISCREG_CPSR];
305 switch (cpsr.mode) {

--- 145 unchanged lines hidden --- 		291 flattenMiscIndex(int reg) const
292 {
293 assert(reg >= 0);
294 int flat_idx = reg;
295
296 if (reg == MISCREG_SPSR) {
297 CPSR cpsr = miscRegs[MISCREG_CPSR];
298 switch (cpsr.mode) {

--- 145 unchanged lines hidden ---