1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 123 unchanged lines hidden (view full) --- 132 } 133 134 int 135 flattenFloatIndex(int reg) 136 { 137 return reg; 138 } 139 |
140 int 141 flattenMiscIndex(int reg) 142 { 143 if (reg == MISCREG_SPSR) { 144 int spsr_idx = NUM_MISCREGS; 145 CPSR cpsr = miscRegs[MISCREG_CPSR]; 146 switch (cpsr.mode) { 147 case MODE_USER: 148 warn("User mode does not have SPSR\n"); 149 spsr_idx = MISCREG_SPSR; 150 break; 151 case MODE_FIQ: 152 spsr_idx = MISCREG_SPSR_FIQ; 153 break; 154 case MODE_IRQ: 155 spsr_idx = MISCREG_SPSR_IRQ; 156 break; 157 case MODE_SVC: 158 spsr_idx = MISCREG_SPSR_SVC; 159 break; 160 case MODE_MON: 161 spsr_idx = MISCREG_SPSR_MON; 162 break; 163 case MODE_ABORT: 164 spsr_idx = MISCREG_SPSR_ABT; 165 break; 166 case MODE_UNDEFINED: 167 spsr_idx = MISCREG_SPSR_UND; 168 break; 169 default: 170 warn("Trying to access SPSR in an invalid mode: %d\n", 171 cpsr.mode); 172 spsr_idx = MISCREG_SPSR; 173 break; 174 } 175 return spsr_idx; 176 } 177 return reg; 178 } 179 |
180 void serialize(EventManager *em, std::ostream &os) 181 {} 182 void unserialize(EventManager *em, Checkpoint *cp, 183 const std::string §ion) 184 {} 185 186 ISA() 187 { 188 SCTLR sctlr; 189 sctlr = 0; 190 miscRegs[MISCREG_SCTLR_RST] = sctlr; 191 192 clear(); 193 } 194 }; 195} 196 197#endif |