1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 27 unchanged lines hidden (view full) --- 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42 43#ifndef __ARCH_ARM_ISA_HH__ |
44#define __ARCH_ARM_ISA_HH__ |
45 46#include "arch/arm/registers.hh" |
47#include "arch/arm/tlb.hh" |
48#include "arch/arm/types.hh" 49 50class ThreadContext; 51class Checkpoint; 52class EventManager; 53 54namespace ArmISA 55{ --- 163 unchanged lines hidden (view full) --- 219 switch (misc_reg) { 220 case MISCREG_CLIDR: 221 warn("The clidr register always reports 0 caches.\n"); 222 break; 223 case MISCREG_CCSIDR: 224 warn("The ccsidr register isn't implemented and " 225 "always reads as 0.\n"); 226 break; |
227 case MISCREG_ID_PFR0: 228 return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM |
229 } 230 return readMiscRegNoEffect(misc_reg); 231 } 232 233 void 234 setMiscRegNoEffect(int misc_reg, const MiscReg &val) 235 { 236 assert(misc_reg < NumMiscRegs); --- 108 unchanged lines hidden (view full) --- 345 return; 346 } 347 case MISCREG_TLBTR: 348 case MISCREG_MVFR0: 349 case MISCREG_MVFR1: 350 case MISCREG_MPIDR: 351 case MISCREG_FPSID: 352 return; |
353 case MISCREG_TLBIALLIS: 354 case MISCREG_TLBIALL: 355 warn("Need to flush all TLBs in MP\n"); 356 tc->getITBPtr()->flushAll(); 357 tc->getDTBPtr()->flushAll(); 358 return; 359 case MISCREG_ITLBIALL: 360 tc->getITBPtr()->flushAll(); 361 return; 362 case MISCREG_DTLBIALL: 363 tc->getDTBPtr()->flushAll(); 364 return; 365 case MISCREG_TLBIMVAIS: 366 case MISCREG_TLBIMVA: 367 warn("Need to flush all TLBs in MP\n"); 368 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 369 bits(newVal, 7,0)); 370 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 371 bits(newVal, 7,0)); 372 return; 373 case MISCREG_TLBIASIDIS: 374 case MISCREG_TLBIASID: 375 warn("Need to flush all TLBs in MP\n"); 376 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 377 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 378 return; 379 case MISCREG_TLBIMVAAIS: 380 case MISCREG_TLBIMVAA: 381 warn("Need to flush all TLBs in MP\n"); 382 tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 383 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 384 return; 385 case MISCREG_ITLBIMVA: 386 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 387 bits(newVal, 7,0)); 388 return; 389 case MISCREG_DTLBIMVA: 390 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 391 bits(newVal, 7,0)); 392 return; 393 case MISCREG_ITLBIASID: 394 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 395 return; 396 case MISCREG_DTLBIASID: 397 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 398 return; |
399 } 400 setMiscRegNoEffect(misc_reg, newVal); 401 } 402 403 int 404 flattenIntIndex(int reg) 405 { 406 assert(reg >= 0); --- 53 unchanged lines hidden --- |