1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 281 unchanged lines hidden (view full) --- 290 panic("Disabling coprocessors isn't implemented.\n"); 291 } 292 newVal = newCpacr; 293 } 294 break; 295 case MISCREG_CSSELR: 296 warn("The csselr register isn't implemented.\n"); 297 break; |
298 case MISCREG_FPSCR: 299 { 300 const uint32_t ones = (uint32_t)(-1); 301 FPSCR fpscrMask = 0; 302 fpscrMask.ioc = ones; 303 fpscrMask.dzc = ones; 304 fpscrMask.ofc = ones; 305 fpscrMask.ufc = ones; 306 fpscrMask.ixc = ones; 307 fpscrMask.idc = ones; 308 fpscrMask.len = ones; 309 fpscrMask.stride = ones; 310 fpscrMask.rMode = ones; 311 fpscrMask.fz = ones; 312 fpscrMask.dn = ones; 313 fpscrMask.ahp = ones; 314 fpscrMask.qc = ones; 315 fpscrMask.v = ones; 316 fpscrMask.c = ones; 317 fpscrMask.z = ones; 318 fpscrMask.n = ones; 319 newVal = (newVal & (uint32_t)fpscrMask) | 320 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 321 } 322 break; 323 case MISCREG_FPEXC: 324 { 325 const uint32_t fpexcMask = 0x60000000; 326 newVal = (newVal & fpexcMask) | 327 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 328 } 329 break; |
330 case MISCREG_TLBTR: 331 case MISCREG_MVFR0: 332 case MISCREG_MVFR1: 333 case MISCREG_MPIDR: |
334 case MISCREG_FPSID: |
335 return; 336 } 337 return setMiscRegNoEffect(misc_reg, newVal); 338 } 339 340 int 341 flattenIntIndex(int reg) 342 { --- 50 unchanged lines hidden --- |