1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 141 unchanged lines hidden (view full) --- 150 mvfr1.defaultNaN = 1; 151 mvfr1.advSimdLoadStore = 1; 152 mvfr1.advSimdInteger = 1; 153 mvfr1.advSimdSinglePrecision = 1; 154 mvfr1.advSimdHalfPrecision = 1; 155 mvfr1.vfpHalfPrecision = 1; 156 miscRegs[MISCREG_MVFR1] = mvfr1; 157 |
158 miscRegs[MISCREG_MPIDR] = 0; 159 |
160 //XXX We need to initialize the rest of the state. 161 } 162 163 MiscReg 164 readMiscRegNoEffect(int misc_reg) 165 { 166 assert(misc_reg < NumMiscRegs); 167 if (misc_reg == MISCREG_SPSR) { --- 125 unchanged lines hidden (view full) --- 293 } 294 break; 295 case MISCREG_CSSELR: 296 warn("The csselr register isn't implemented.\n"); 297 break; 298 case MISCREG_TLBTR: 299 case MISCREG_MVFR0: 300 case MISCREG_MVFR1: |
301 case MISCREG_MPIDR: |
302 return; 303 } 304 return setMiscRegNoEffect(misc_reg, newVal); 305 } 306 307 int 308 flattenIntIndex(int reg) 309 { --- 50 unchanged lines hidden --- |