1/* 2 * Copyright (c) 2010, 2012-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43#ifndef __ARCH_ARM_ISA_HH__ 44#define __ARCH_ARM_ISA_HH__ 45 46#include "arch/arm/isa_device.hh" 47#include "arch/arm/registers.hh" 48#include "arch/arm/system.hh" 49#include "arch/arm/tlb.hh" 50#include "arch/arm/types.hh" |
51#include "arch/generic/traits.hh" |
52#include "debug/Checkpoint.hh" |
53#include "enums/VecRegRenameMode.hh" |
54#include "sim/sim_object.hh" 55#include "enums/DecoderFlavour.hh" 56 57struct ArmISAParams; 58struct DummyArmISADeviceParams; 59class ThreadContext; 60class Checkpoint; 61class EventManager; 62 63namespace ArmISA 64{ 65 class ISA : public SimObject 66 { 67 protected: 68 // Parent system 69 ArmSystem *system; 70 71 // Micro Architecture 72 const Enums::DecoderFlavour _decoderFlavour; |
73 const Enums::VecRegRenameMode _vecRegRenameMode; |
74 75 /** Dummy device for to handle non-existing ISA devices */ 76 DummyISADevice dummyDevice; 77 78 // PMU belonging to this ISA 79 BaseISADevice *pmu; 80 81 // Generic timer interface belonging to this ISA --- 101 unchanged lines hidden (view full) --- 183 RegId 184 flattenRegId(const RegId& regId) const 185 { 186 switch (regId.classValue()) { 187 case IntRegClass: 188 return RegId(IntRegClass, flattenIntIndex(regId.index())); 189 case FloatRegClass: 190 return RegId(FloatRegClass, flattenFloatIndex(regId.index())); |
191 case VecRegClass: 192 return RegId(VecRegClass, flattenVecIndex(regId.index())); 193 case VecElemClass: 194 return RegId(VecElemClass, flattenVecElemIndex(regId.index())); |
195 case CCRegClass: 196 return RegId(CCRegClass, flattenCCIndex(regId.index())); 197 case MiscRegClass: 198 return RegId(MiscRegClass, flattenMiscIndex(regId.index())); 199 } 200 return RegId(); 201 } 202 --- 32 unchanged lines hidden (view full) --- 235 int 236 flattenFloatIndex(int reg) const 237 { 238 assert(reg >= 0); 239 return reg; 240 } 241 242 int |
243 flattenVecIndex(int reg) const 244 { 245 assert(reg >= 0); 246 return reg; 247 } 248 249 int 250 flattenVecElemIndex(int reg) const 251 { 252 assert(reg >= 0); 253 return reg; 254 } 255 256 int |
257 flattenCCIndex(int reg) const 258 { 259 assert(reg >= 0); 260 return reg; 261 } 262 263 int 264 flattenMiscIndex(int reg) const --- 157 unchanged lines hidden (view full) --- 422 UNSERIALIZE_SCALAR(haveLargeAsid64); 423 UNSERIALIZE_SCALAR(physAddrRange64); 424 } 425 426 void startup(ThreadContext *tc) {} 427 428 Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; } 429 |
430 Enums::VecRegRenameMode 431 vecRegRenameMode() const 432 { 433 return _vecRegRenameMode; 434 } 435 |
436 /// Explicitly import the otherwise hidden startup 437 using SimObject::startup; 438 439 typedef ArmISAParams Params; 440 441 const Params *params() const; 442 443 ISA(Params *p); 444 }; 445} 446 |
447template<> 448struct initRenameMode<ArmISA::ISA> 449{ 450 static Enums::VecRegRenameMode mode(const ArmISA::ISA* isa) 451 { 452 return isa->vecRegRenameMode(); 453 } 454 static bool equals(const ArmISA::ISA* isa1, const ArmISA::ISA* isa2) 455 { 456 return mode(isa1) == mode(isa2); 457 } 458}; 459 |
460#endif |