1/* 2 * Copyright (c) 2010, 2012-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 29 unchanged lines hidden (view full) --- 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42 43#ifndef __ARCH_ARM_ISA_HH__ 44#define __ARCH_ARM_ISA_HH__ 45 |
46#include "arch/arm/isa_device.hh" |
47#include "arch/arm/registers.hh" 48#include "arch/arm/system.hh" 49#include "arch/arm/tlb.hh" 50#include "arch/arm/types.hh" 51#include "debug/Checkpoint.hh" 52#include "dev/arm/generic_timer.hh" 53#include "sim/sim_object.hh" 54 55struct ArmISAParams; |
56struct DummyArmISADeviceParams; |
57class ThreadContext; 58class Checkpoint; 59class EventManager; 60 61namespace ArmISA 62{ 63 64 /** --- 63 unchanged lines hidden (view full) --- 128 }; 129 130 class ISA : public SimObject 131 { 132 protected: 133 // Parent system 134 ArmSystem *system; 135 |
136 /** Dummy device for to handle non-existing ISA devices */ 137 DummyISADevice dummyDevice; 138 139 // PMU belonging to this ISA 140 BaseISADevice *pmu; 141 |
142 // Cached copies of system-level properties 143 bool haveSecurity; 144 bool haveLPAE; 145 bool haveVirtualization; 146 bool haveLargeAsid64; 147 uint8_t physAddrRange64; 148 149 /** Register translation entry used in lookUpMiscReg */ --- 294 unchanged lines hidden --- |