1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_ARM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/types.hh"
49#include "debug/Checkpoint.hh"
50#include "sim/sim_object.hh"
51
52struct ArmISAParams;
53class ThreadContext;
54class Checkpoint;
55class EventManager;
56
57namespace ArmISA
58{
59 class ISA : public SimObject
60 {
61 protected:
62 MiscReg miscRegs[NumMiscRegs];
63 const IntRegIndex *intRegMap;
64
65 void
66 updateRegMap(CPSR cpsr)
67 {
68 switch (cpsr.mode) {
69 case MODE_USER:
70 case MODE_SYSTEM:
71 intRegMap = IntRegUsrMap;
72 break;
73 case MODE_FIQ:
74 intRegMap = IntRegFiqMap;
75 break;
76 case MODE_IRQ:
77 intRegMap = IntRegIrqMap;
78 break;
79 case MODE_SVC:
80 intRegMap = IntRegSvcMap;
81 break;
82 case MODE_MON:
83 intRegMap = IntRegMonMap;
84 break;
85 case MODE_ABORT:
86 intRegMap = IntRegAbtMap;
87 break;
88 case MODE_UNDEFINED:
89 intRegMap = IntRegUndMap;
90 break;
91 default:
92 panic("Unrecognized mode setting in CPSR.\n");
93 }
94 }
95
96 public:
97 void clear();
98
99 MiscReg readMiscRegNoEffect(int misc_reg);
100 MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
101 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
102 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
103
104 int
105 flattenIntIndex(int reg)
106 {
107 assert(reg >= 0);
108 if (reg < NUM_ARCH_INTREGS) {
109 return intRegMap[reg];
110 } else if (reg < NUM_INTREGS) {
111 return reg;
112 } else {
113 int mode = reg / intRegsPerMode;
114 reg = reg % intRegsPerMode;
115 switch (mode) {
116 case MODE_USER:
117 case MODE_SYSTEM:
118 return INTREG_USR(reg);
119 case MODE_FIQ:
120 return INTREG_FIQ(reg);
121 case MODE_IRQ:
122 return INTREG_IRQ(reg);
123 case MODE_SVC:
124 return INTREG_SVC(reg);
125 case MODE_MON:
126 return INTREG_MON(reg);
127 case MODE_ABORT:
128 return INTREG_ABT(reg);
129 case MODE_UNDEFINED:
130 return INTREG_UND(reg);
131 default:
132 panic("Flattening into an unknown mode.\n");
133 }
134 }
135 }
136
137 int
138 flattenFloatIndex(int reg)
139 {
140 return reg;
141 }
142
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_ARM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/types.hh"
49#include "debug/Checkpoint.hh"
50#include "sim/sim_object.hh"
51
52struct ArmISAParams;
53class ThreadContext;
54class Checkpoint;
55class EventManager;
56
57namespace ArmISA
58{
59 class ISA : public SimObject
60 {
61 protected:
62 MiscReg miscRegs[NumMiscRegs];
63 const IntRegIndex *intRegMap;
64
65 void
66 updateRegMap(CPSR cpsr)
67 {
68 switch (cpsr.mode) {
69 case MODE_USER:
70 case MODE_SYSTEM:
71 intRegMap = IntRegUsrMap;
72 break;
73 case MODE_FIQ:
74 intRegMap = IntRegFiqMap;
75 break;
76 case MODE_IRQ:
77 intRegMap = IntRegIrqMap;
78 break;
79 case MODE_SVC:
80 intRegMap = IntRegSvcMap;
81 break;
82 case MODE_MON:
83 intRegMap = IntRegMonMap;
84 break;
85 case MODE_ABORT:
86 intRegMap = IntRegAbtMap;
87 break;
88 case MODE_UNDEFINED:
89 intRegMap = IntRegUndMap;
90 break;
91 default:
92 panic("Unrecognized mode setting in CPSR.\n");
93 }
94 }
95
96 public:
97 void clear();
98
99 MiscReg readMiscRegNoEffect(int misc_reg);
100 MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
101 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
102 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
103
104 int
105 flattenIntIndex(int reg)
106 {
107 assert(reg >= 0);
108 if (reg < NUM_ARCH_INTREGS) {
109 return intRegMap[reg];
110 } else if (reg < NUM_INTREGS) {
111 return reg;
112 } else {
113 int mode = reg / intRegsPerMode;
114 reg = reg % intRegsPerMode;
115 switch (mode) {
116 case MODE_USER:
117 case MODE_SYSTEM:
118 return INTREG_USR(reg);
119 case MODE_FIQ:
120 return INTREG_FIQ(reg);
121 case MODE_IRQ:
122 return INTREG_IRQ(reg);
123 case MODE_SVC:
124 return INTREG_SVC(reg);
125 case MODE_MON:
126 return INTREG_MON(reg);
127 case MODE_ABORT:
128 return INTREG_ABT(reg);
129 case MODE_UNDEFINED:
130 return INTREG_UND(reg);
131 default:
132 panic("Flattening into an unknown mode.\n");
133 }
134 }
135 }
136
137 int
138 flattenFloatIndex(int reg)
139 {
140 return reg;
141 }
142
|
144 flattenMiscIndex(int reg)
145 {
146 if (reg == MISCREG_SPSR) {
147 int spsr_idx = NUM_MISCREGS;
148 CPSR cpsr = miscRegs[MISCREG_CPSR];
149 switch (cpsr.mode) {
150 case MODE_USER:
151 warn("User mode does not have SPSR\n");
152 spsr_idx = MISCREG_SPSR;
153 break;
154 case MODE_FIQ:
155 spsr_idx = MISCREG_SPSR_FIQ;
156 break;
157 case MODE_IRQ:
158 spsr_idx = MISCREG_SPSR_IRQ;
159 break;
160 case MODE_SVC:
161 spsr_idx = MISCREG_SPSR_SVC;
162 break;
163 case MODE_MON:
164 spsr_idx = MISCREG_SPSR_MON;
165 break;
166 case MODE_ABORT:
167 spsr_idx = MISCREG_SPSR_ABT;
168 break;
169 case MODE_UNDEFINED:
170 spsr_idx = MISCREG_SPSR_UND;
171 break;
172 default:
173 warn("Trying to access SPSR in an invalid mode: %d\n",
174 cpsr.mode);
175 spsr_idx = MISCREG_SPSR;
176 break;
177 }
178 return spsr_idx;
179 }
180 return reg;
181 }
182
183 void serialize(std::ostream &os)
184 {
185 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
186 SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
187 }
188 void unserialize(Checkpoint *cp, const std::string §ion)
189 {
190 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
191 UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
192 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
193 updateRegMap(tmp_cpsr);
194 }
195
196 void startup(ThreadContext *tc) {}
197
198 /// Explicitly import the otherwise hidden startup
199 using SimObject::startup;
200
201 typedef ArmISAParams Params;
202
203 const Params *params() const;
204
205 ISA(Params *p);
206 };
207}
208
209#endif
| 151 flattenMiscIndex(int reg)
152 {
153 if (reg == MISCREG_SPSR) {
154 int spsr_idx = NUM_MISCREGS;
155 CPSR cpsr = miscRegs[MISCREG_CPSR];
156 switch (cpsr.mode) {
157 case MODE_USER:
158 warn("User mode does not have SPSR\n");
159 spsr_idx = MISCREG_SPSR;
160 break;
161 case MODE_FIQ:
162 spsr_idx = MISCREG_SPSR_FIQ;
163 break;
164 case MODE_IRQ:
165 spsr_idx = MISCREG_SPSR_IRQ;
166 break;
167 case MODE_SVC:
168 spsr_idx = MISCREG_SPSR_SVC;
169 break;
170 case MODE_MON:
171 spsr_idx = MISCREG_SPSR_MON;
172 break;
173 case MODE_ABORT:
174 spsr_idx = MISCREG_SPSR_ABT;
175 break;
176 case MODE_UNDEFINED:
177 spsr_idx = MISCREG_SPSR_UND;
178 break;
179 default:
180 warn("Trying to access SPSR in an invalid mode: %d\n",
181 cpsr.mode);
182 spsr_idx = MISCREG_SPSR;
183 break;
184 }
185 return spsr_idx;
186 }
187 return reg;
188 }
189
190 void serialize(std::ostream &os)
191 {
192 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
193 SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
194 }
195 void unserialize(Checkpoint *cp, const std::string §ion)
196 {
197 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
198 UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
199 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
200 updateRegMap(tmp_cpsr);
201 }
202
203 void startup(ThreadContext *tc) {}
204
205 /// Explicitly import the otherwise hidden startup
206 using SimObject::startup;
207
208 typedef ArmISAParams Params;
209
210 const Params *params() const;
211
212 ISA(Params *p);
213 };
214}
215
216#endif
|