isa.hh (7348:c8103c298d68) isa.hh (7350:41e3ee23125e)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_MRM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/types.hh"
48
49class ThreadContext;
50class Checkpoint;
51class EventManager;
52
53namespace ArmISA
54{
55 class ISA
56 {
57 protected:
58 MiscReg miscRegs[NumMiscRegs];
59 const IntRegIndex *intRegMap;
60
61 void
62 updateRegMap(CPSR cpsr)
63 {
64 switch (cpsr.mode) {
65 case MODE_USER:
66 case MODE_SYSTEM:
67 intRegMap = IntRegUsrMap;
68 break;
69 case MODE_FIQ:
70 intRegMap = IntRegFiqMap;
71 break;
72 case MODE_IRQ:
73 intRegMap = IntRegIrqMap;
74 break;
75 case MODE_SVC:
76 intRegMap = IntRegSvcMap;
77 break;
78 case MODE_MON:
79 intRegMap = IntRegMonMap;
80 break;
81 case MODE_ABORT:
82 intRegMap = IntRegAbtMap;
83 break;
84 case MODE_UNDEFINED:
85 intRegMap = IntRegUndMap;
86 break;
87 default:
88 panic("Unrecognized mode setting in CPSR.\n");
89 }
90 }
91
92 public:
93 void clear()
94 {
95 memset(miscRegs, 0, sizeof(miscRegs));
96 CPSR cpsr = 0;
97 cpsr.mode = MODE_USER;
98 miscRegs[MISCREG_CPSR] = cpsr;
99 updateRegMap(cpsr);
100
101 SCTLR sctlr = 0;
102 sctlr.nmfi = 1;
103 sctlr.rao1 = 1;
104 sctlr.rao2 = 1;
105 sctlr.rao3 = 1;
106 sctlr.rao4 = 1;
107 miscRegs[MISCREG_SCTLR] = sctlr;
108
109 /*
110 * Technically this should be 0, but we don't support those
111 * settings.
112 */
113 CPACR cpacr = 0;
114 // Enable CP 10, 11
115 cpacr.cp10 = 0x3;
116 cpacr.cp11 = 0x3;
117 miscRegs[MISCREG_CPACR] = cpacr;
118
119 /* One region, unified map. */
120 miscRegs[MISCREG_MPUIR] = 0x100;
121
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_MRM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/types.hh"
48
49class ThreadContext;
50class Checkpoint;
51class EventManager;
52
53namespace ArmISA
54{
55 class ISA
56 {
57 protected:
58 MiscReg miscRegs[NumMiscRegs];
59 const IntRegIndex *intRegMap;
60
61 void
62 updateRegMap(CPSR cpsr)
63 {
64 switch (cpsr.mode) {
65 case MODE_USER:
66 case MODE_SYSTEM:
67 intRegMap = IntRegUsrMap;
68 break;
69 case MODE_FIQ:
70 intRegMap = IntRegFiqMap;
71 break;
72 case MODE_IRQ:
73 intRegMap = IntRegIrqMap;
74 break;
75 case MODE_SVC:
76 intRegMap = IntRegSvcMap;
77 break;
78 case MODE_MON:
79 intRegMap = IntRegMonMap;
80 break;
81 case MODE_ABORT:
82 intRegMap = IntRegAbtMap;
83 break;
84 case MODE_UNDEFINED:
85 intRegMap = IntRegUndMap;
86 break;
87 default:
88 panic("Unrecognized mode setting in CPSR.\n");
89 }
90 }
91
92 public:
93 void clear()
94 {
95 memset(miscRegs, 0, sizeof(miscRegs));
96 CPSR cpsr = 0;
97 cpsr.mode = MODE_USER;
98 miscRegs[MISCREG_CPSR] = cpsr;
99 updateRegMap(cpsr);
100
101 SCTLR sctlr = 0;
102 sctlr.nmfi = 1;
103 sctlr.rao1 = 1;
104 sctlr.rao2 = 1;
105 sctlr.rao3 = 1;
106 sctlr.rao4 = 1;
107 miscRegs[MISCREG_SCTLR] = sctlr;
108
109 /*
110 * Technically this should be 0, but we don't support those
111 * settings.
112 */
113 CPACR cpacr = 0;
114 // Enable CP 10, 11
115 cpacr.cp10 = 0x3;
116 cpacr.cp11 = 0x3;
117 miscRegs[MISCREG_CPACR] = cpacr;
118
119 /* One region, unified map. */
120 miscRegs[MISCREG_MPUIR] = 0x100;
121
122 /* Start with an event in the mailbox */
123 miscRegs[MISCREG_SEV_MAILBOX] = 1;
124
122 /*
123 * Implemented = '5' from "M5",
124 * Variant = 0,
125 */
126 miscRegs[MISCREG_MIDR] =
127 (0x35 << 24) | //Implementor is '5' from "M5"
128 (0 << 20) | //Variant
129 (0xf << 16) | //Architecture from CPUID scheme
130 (0 << 4) | //Primary part number
131 (0 << 0) | //Revision
132 0;
133
134 //XXX We need to initialize the rest of the state.
135 }
136
137 MiscReg
138 readMiscRegNoEffect(int misc_reg)
139 {
140 assert(misc_reg < NumMiscRegs);
141 if (misc_reg == MISCREG_SPSR) {
142 CPSR cpsr = miscRegs[MISCREG_CPSR];
143 switch (cpsr.mode) {
144 case MODE_USER:
145 return miscRegs[MISCREG_SPSR];
146 case MODE_FIQ:
147 return miscRegs[MISCREG_SPSR_FIQ];
148 case MODE_IRQ:
149 return miscRegs[MISCREG_SPSR_IRQ];
150 case MODE_SVC:
151 return miscRegs[MISCREG_SPSR_SVC];
152 case MODE_MON:
153 return miscRegs[MISCREG_SPSR_MON];
154 case MODE_ABORT:
155 return miscRegs[MISCREG_SPSR_ABT];
156 case MODE_UNDEFINED:
157 return miscRegs[MISCREG_SPSR_UND];
158 default:
159 return miscRegs[MISCREG_SPSR];
160 }
161 }
162 return miscRegs[misc_reg];
163 }
164
165 MiscReg
166 readMiscReg(int misc_reg, ThreadContext *tc)
167 {
168 if (misc_reg == MISCREG_CPSR) {
169 CPSR cpsr = miscRegs[misc_reg];
170 Addr pc = tc->readPC();
171 if (pc & (ULL(1) << PcJBitShift))
172 cpsr.j = 1;
173 else
174 cpsr.j = 0;
175 if (pc & (ULL(1) << PcTBitShift))
176 cpsr.t = 1;
177 else
178 cpsr.t = 0;
179 return cpsr;
180 }
181 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
182 misc_reg < MISCREG_CP15_END) {
183 panic("Unimplemented CP15 register %s read.\n",
184 miscRegName[misc_reg]);
185 }
186 switch (misc_reg) {
187 case MISCREG_CLIDR:
188 warn("The clidr register always reports 0 caches.\n");
189 break;
190 case MISCREG_CCSIDR:
191 warn("The ccsidr register isn't implemented and "
192 "always reads as 0.\n");
193 break;
194 }
195 return readMiscRegNoEffect(misc_reg);
196 }
197
198 void
199 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
200 {
201 assert(misc_reg < NumMiscRegs);
202 if (misc_reg == MISCREG_SPSR) {
203 CPSR cpsr = miscRegs[MISCREG_CPSR];
204 switch (cpsr.mode) {
205 case MODE_USER:
206 miscRegs[MISCREG_SPSR] = val;
207 return;
208 case MODE_FIQ:
209 miscRegs[MISCREG_SPSR_FIQ] = val;
210 return;
211 case MODE_IRQ:
212 miscRegs[MISCREG_SPSR_IRQ] = val;
213 return;
214 case MODE_SVC:
215 miscRegs[MISCREG_SPSR_SVC] = val;
216 return;
217 case MODE_MON:
218 miscRegs[MISCREG_SPSR_MON] = val;
219 return;
220 case MODE_ABORT:
221 miscRegs[MISCREG_SPSR_ABT] = val;
222 return;
223 case MODE_UNDEFINED:
224 miscRegs[MISCREG_SPSR_UND] = val;
225 return;
226 default:
227 miscRegs[MISCREG_SPSR] = val;
228 return;
229 }
230 }
231 miscRegs[misc_reg] = val;
232 }
233
234 void
235 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
236 {
237 MiscReg newVal = val;
238 if (misc_reg == MISCREG_CPSR) {
239 updateRegMap(val);
240 CPSR cpsr = val;
241 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
242 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
243 Addr npc = tc->readNextPC() & ~PcModeMask;
244 if (cpsr.j)
245 npc = npc | (ULL(1) << PcJBitShift);
246 if (cpsr.t)
247 npc = npc | (ULL(1) << PcTBitShift);
248
249 tc->setNextPC(npc);
250 }
251 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
252 misc_reg < MISCREG_CP15_END) {
253 panic("Unimplemented CP15 register %s wrote with %#x.\n",
254 miscRegName[misc_reg], val);
255 }
256 switch (misc_reg) {
257 case MISCREG_CPACR:
258 {
259 CPACR newCpacr = 0;
260 CPACR valCpacr = val;
261 newCpacr.cp10 = valCpacr.cp10;
262 newCpacr.cp11 = valCpacr.cp11;
263 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
264 panic("Disabling coprocessors isn't implemented.\n");
265 }
266 newVal = newCpacr;
267 }
268 break;
269 case MISCREG_CSSELR:
270 warn("The csselr register isn't implemented.\n");
271 break;
272 }
273 return setMiscRegNoEffect(misc_reg, newVal);
274 }
275
276 int
277 flattenIntIndex(int reg)
278 {
279 assert(reg >= 0);
280 if (reg < NUM_ARCH_INTREGS) {
281 return intRegMap[reg];
282 } else if (reg < NUM_INTREGS) {
283 return reg;
284 } else {
285 int mode = reg / intRegsPerMode;
286 reg = reg % intRegsPerMode;
287 switch (mode) {
288 case MODE_USER:
289 case MODE_SYSTEM:
290 return INTREG_USR(reg);
291 case MODE_FIQ:
292 return INTREG_FIQ(reg);
293 case MODE_IRQ:
294 return INTREG_IRQ(reg);
295 case MODE_SVC:
296 return INTREG_SVC(reg);
297 case MODE_MON:
298 return INTREG_MON(reg);
299 case MODE_ABORT:
300 return INTREG_ABT(reg);
301 case MODE_UNDEFINED:
302 return INTREG_UND(reg);
303 default:
304 panic("Flattening into an unknown mode.\n");
305 }
306 }
307 }
308
309 int
310 flattenFloatIndex(int reg)
311 {
312 return reg;
313 }
314
315 void serialize(EventManager *em, std::ostream &os)
316 {}
317 void unserialize(EventManager *em, Checkpoint *cp,
318 const std::string &section)
319 {}
320
321 ISA()
322 {
323 clear();
324 }
325 };
326}
327
328#endif
125 /*
126 * Implemented = '5' from "M5",
127 * Variant = 0,
128 */
129 miscRegs[MISCREG_MIDR] =
130 (0x35 << 24) | //Implementor is '5' from "M5"
131 (0 << 20) | //Variant
132 (0xf << 16) | //Architecture from CPUID scheme
133 (0 << 4) | //Primary part number
134 (0 << 0) | //Revision
135 0;
136
137 //XXX We need to initialize the rest of the state.
138 }
139
140 MiscReg
141 readMiscRegNoEffect(int misc_reg)
142 {
143 assert(misc_reg < NumMiscRegs);
144 if (misc_reg == MISCREG_SPSR) {
145 CPSR cpsr = miscRegs[MISCREG_CPSR];
146 switch (cpsr.mode) {
147 case MODE_USER:
148 return miscRegs[MISCREG_SPSR];
149 case MODE_FIQ:
150 return miscRegs[MISCREG_SPSR_FIQ];
151 case MODE_IRQ:
152 return miscRegs[MISCREG_SPSR_IRQ];
153 case MODE_SVC:
154 return miscRegs[MISCREG_SPSR_SVC];
155 case MODE_MON:
156 return miscRegs[MISCREG_SPSR_MON];
157 case MODE_ABORT:
158 return miscRegs[MISCREG_SPSR_ABT];
159 case MODE_UNDEFINED:
160 return miscRegs[MISCREG_SPSR_UND];
161 default:
162 return miscRegs[MISCREG_SPSR];
163 }
164 }
165 return miscRegs[misc_reg];
166 }
167
168 MiscReg
169 readMiscReg(int misc_reg, ThreadContext *tc)
170 {
171 if (misc_reg == MISCREG_CPSR) {
172 CPSR cpsr = miscRegs[misc_reg];
173 Addr pc = tc->readPC();
174 if (pc & (ULL(1) << PcJBitShift))
175 cpsr.j = 1;
176 else
177 cpsr.j = 0;
178 if (pc & (ULL(1) << PcTBitShift))
179 cpsr.t = 1;
180 else
181 cpsr.t = 0;
182 return cpsr;
183 }
184 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
185 misc_reg < MISCREG_CP15_END) {
186 panic("Unimplemented CP15 register %s read.\n",
187 miscRegName[misc_reg]);
188 }
189 switch (misc_reg) {
190 case MISCREG_CLIDR:
191 warn("The clidr register always reports 0 caches.\n");
192 break;
193 case MISCREG_CCSIDR:
194 warn("The ccsidr register isn't implemented and "
195 "always reads as 0.\n");
196 break;
197 }
198 return readMiscRegNoEffect(misc_reg);
199 }
200
201 void
202 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
203 {
204 assert(misc_reg < NumMiscRegs);
205 if (misc_reg == MISCREG_SPSR) {
206 CPSR cpsr = miscRegs[MISCREG_CPSR];
207 switch (cpsr.mode) {
208 case MODE_USER:
209 miscRegs[MISCREG_SPSR] = val;
210 return;
211 case MODE_FIQ:
212 miscRegs[MISCREG_SPSR_FIQ] = val;
213 return;
214 case MODE_IRQ:
215 miscRegs[MISCREG_SPSR_IRQ] = val;
216 return;
217 case MODE_SVC:
218 miscRegs[MISCREG_SPSR_SVC] = val;
219 return;
220 case MODE_MON:
221 miscRegs[MISCREG_SPSR_MON] = val;
222 return;
223 case MODE_ABORT:
224 miscRegs[MISCREG_SPSR_ABT] = val;
225 return;
226 case MODE_UNDEFINED:
227 miscRegs[MISCREG_SPSR_UND] = val;
228 return;
229 default:
230 miscRegs[MISCREG_SPSR] = val;
231 return;
232 }
233 }
234 miscRegs[misc_reg] = val;
235 }
236
237 void
238 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
239 {
240 MiscReg newVal = val;
241 if (misc_reg == MISCREG_CPSR) {
242 updateRegMap(val);
243 CPSR cpsr = val;
244 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
245 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
246 Addr npc = tc->readNextPC() & ~PcModeMask;
247 if (cpsr.j)
248 npc = npc | (ULL(1) << PcJBitShift);
249 if (cpsr.t)
250 npc = npc | (ULL(1) << PcTBitShift);
251
252 tc->setNextPC(npc);
253 }
254 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
255 misc_reg < MISCREG_CP15_END) {
256 panic("Unimplemented CP15 register %s wrote with %#x.\n",
257 miscRegName[misc_reg], val);
258 }
259 switch (misc_reg) {
260 case MISCREG_CPACR:
261 {
262 CPACR newCpacr = 0;
263 CPACR valCpacr = val;
264 newCpacr.cp10 = valCpacr.cp10;
265 newCpacr.cp11 = valCpacr.cp11;
266 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
267 panic("Disabling coprocessors isn't implemented.\n");
268 }
269 newVal = newCpacr;
270 }
271 break;
272 case MISCREG_CSSELR:
273 warn("The csselr register isn't implemented.\n");
274 break;
275 }
276 return setMiscRegNoEffect(misc_reg, newVal);
277 }
278
279 int
280 flattenIntIndex(int reg)
281 {
282 assert(reg >= 0);
283 if (reg < NUM_ARCH_INTREGS) {
284 return intRegMap[reg];
285 } else if (reg < NUM_INTREGS) {
286 return reg;
287 } else {
288 int mode = reg / intRegsPerMode;
289 reg = reg % intRegsPerMode;
290 switch (mode) {
291 case MODE_USER:
292 case MODE_SYSTEM:
293 return INTREG_USR(reg);
294 case MODE_FIQ:
295 return INTREG_FIQ(reg);
296 case MODE_IRQ:
297 return INTREG_IRQ(reg);
298 case MODE_SVC:
299 return INTREG_SVC(reg);
300 case MODE_MON:
301 return INTREG_MON(reg);
302 case MODE_ABORT:
303 return INTREG_ABT(reg);
304 case MODE_UNDEFINED:
305 return INTREG_UND(reg);
306 default:
307 panic("Flattening into an unknown mode.\n");
308 }
309 }
310 }
311
312 int
313 flattenFloatIndex(int reg)
314 {
315 return reg;
316 }
317
318 void serialize(EventManager *em, std::ostream &os)
319 {}
320 void unserialize(EventManager *em, Checkpoint *cp,
321 const std::string &section)
322 {}
323
324 ISA()
325 {
326 clear();
327 }
328 };
329}
330
331#endif