1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_MRM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/types.hh"
48
49class ThreadContext;
50class Checkpoint;
51class EventManager;
52
53namespace ArmISA
54{
55 class ISA
56 {
57 protected:
58 MiscReg miscRegs[NumMiscRegs];
59 const IntRegIndex *intRegMap;
60
61 void
62 updateRegMap(CPSR cpsr)
63 {
64 switch (cpsr.mode) {
65 case MODE_USER:
66 case MODE_SYSTEM:
67 intRegMap = IntRegUsrMap;
68 break;
69 case MODE_FIQ:
70 intRegMap = IntRegFiqMap;
71 break;
72 case MODE_IRQ:
73 intRegMap = IntRegIrqMap;
74 break;
75 case MODE_SVC:
76 intRegMap = IntRegSvcMap;
77 break;
78 case MODE_MON:
79 intRegMap = IntRegMonMap;
80 break;
81 case MODE_ABORT:
82 intRegMap = IntRegAbtMap;
83 break;
84 case MODE_UNDEFINED:
85 intRegMap = IntRegUndMap;
86 break;
87 default:
88 panic("Unrecognized mode setting in CPSR.\n");
89 }
90 }
91
92 public:
93 void clear()
94 {
95 memset(miscRegs, 0, sizeof(miscRegs));
96 CPSR cpsr = 0;
97 cpsr.mode = MODE_USER;
98 miscRegs[MISCREG_CPSR] = cpsr;
99 updateRegMap(cpsr);
100
101 SCTLR sctlr = 0;
102 sctlr.nmfi = 1;
103 sctlr.rao1 = 1;
104 sctlr.rao2 = 1;
105 sctlr.rao3 = 1;
106 sctlr.rao4 = 1;
107 miscRegs[MISCREG_SCTLR] = sctlr;
108
109 /*
110 * Technically this should be 0, but we don't support those
111 * settings.
112 */
113 miscRegs[MISCREG_CPACR] = 0x0fffffff;
114
115 /* One region, unified map. */
116 miscRegs[MISCREG_MPUIR] = 0x100;
117
118 /*
119 * Implemented = '5' from "M5",
120 * Variant = 0,
121 */
122 miscRegs[MISCREG_MIDR] =
123 (0x35 << 24) | //Implementor is '5' from "M5"
124 (0 << 20) | //Variant
125 (0xf << 16) | //Architecture from CPUID scheme
126 (0 << 4) | //Primary part number
127 (0 << 0) | //Revision
128 0;
129
130 //XXX We need to initialize the rest of the state.
131 }
132
133 MiscReg
134 readMiscRegNoEffect(int misc_reg)
135 {
136 assert(misc_reg < NumMiscRegs);
137 if (misc_reg == MISCREG_SPSR) {
138 CPSR cpsr = miscRegs[MISCREG_CPSR];
139 switch (cpsr.mode) {
140 case MODE_USER:
141 return miscRegs[MISCREG_SPSR];
142 case MODE_FIQ:
143 return miscRegs[MISCREG_SPSR_FIQ];
144 case MODE_IRQ:
145 return miscRegs[MISCREG_SPSR_IRQ];
146 case MODE_SVC:
147 return miscRegs[MISCREG_SPSR_SVC];
148 case MODE_MON:
149 return miscRegs[MISCREG_SPSR_MON];
150 case MODE_ABORT:
151 return miscRegs[MISCREG_SPSR_ABT];
152 case MODE_UNDEFINED:
153 return miscRegs[MISCREG_SPSR_UND];
154 default:
155 return miscRegs[MISCREG_SPSR];
156 }
157 }
158 return miscRegs[misc_reg];
159 }
160
161 MiscReg
162 readMiscReg(int misc_reg, ThreadContext *tc)
163 {
164 if (misc_reg == MISCREG_CPSR) {
165 CPSR cpsr = miscRegs[misc_reg];
166 Addr pc = tc->readPC();
167 if (pc & (ULL(1) << PcJBitShift))
168 cpsr.j = 1;
169 else
170 cpsr.j = 0;
171 if (pc & (ULL(1) << PcTBitShift))
172 cpsr.t = 1;
173 else
174 cpsr.t = 0;
175 return cpsr;
176 }
177 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
178 misc_reg < MISCREG_CP15_END) {
179 panic("Unimplemented CP15 register %s read.\n",
180 miscRegName[misc_reg]);
181 }
182 switch (misc_reg) {
183 case MISCREG_CLIDR:
184 warn("The clidr register always reports 0 caches.\n");
185 break;
186 case MISCREG_CCSIDR:
187 warn("The ccsidr register isn't implemented and "
188 "always reads as 0.\n");
189 break;
190 }
191 return readMiscRegNoEffect(misc_reg);
192 }
193
194 void
195 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
196 {
197 assert(misc_reg < NumMiscRegs);
198 if (misc_reg == MISCREG_SPSR) {
199 CPSR cpsr = miscRegs[MISCREG_CPSR];
200 switch (cpsr.mode) {
201 case MODE_USER:
202 miscRegs[MISCREG_SPSR] = val;
203 return;
204 case MODE_FIQ:
205 miscRegs[MISCREG_SPSR_FIQ] = val;
206 return;
207 case MODE_IRQ:
208 miscRegs[MISCREG_SPSR_IRQ] = val;
209 return;
210 case MODE_SVC:
211 miscRegs[MISCREG_SPSR_SVC] = val;
212 return;
213 case MODE_MON:
214 miscRegs[MISCREG_SPSR_MON] = val;
215 return;
216 case MODE_ABORT:
217 miscRegs[MISCREG_SPSR_ABT] = val;
218 return;
219 case MODE_UNDEFINED:
220 miscRegs[MISCREG_SPSR_UND] = val;
221 return;
222 default:
223 miscRegs[MISCREG_SPSR] = val;
224 return;
225 }
226 }
227 miscRegs[misc_reg] = val;
228 }
229
230 void
231 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
232 {
233 MiscReg newVal = val;
234 if (misc_reg == MISCREG_CPSR) {
235 updateRegMap(val);
236 CPSR cpsr = val;
237 Addr npc = tc->readNextPC() & ~PcModeMask;
238 if (cpsr.j)
239 npc = npc | (ULL(1) << PcJBitShift);
240 if (cpsr.t)
241 npc = npc | (ULL(1) << PcTBitShift);
242
243 tc->setNextPC(npc);
244 }
245 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
246 misc_reg < MISCREG_CP15_END) {
247 panic("Unimplemented CP15 register %s wrote with %#x.\n",
248 miscRegName[misc_reg], val);
249 }
250 switch (misc_reg) {
251 case MISCREG_CPACR:
252 newVal = bits(val, 27, 0);
253 if (newVal != 0x0fffffff) {
254 panic("Disabling coprocessors isn't implemented.\n");
255 }
256 break;
257 case MISCREG_CSSELR:
258 warn("The csselr register isn't implemented.\n");
259 break;
260 }
261 return setMiscRegNoEffect(misc_reg, newVal);
262 }
263
264 int
265 flattenIntIndex(int reg)
266 {
267 assert(reg >= 0);
268 if (reg < NUM_ARCH_INTREGS) {
269 return intRegMap[reg];
270 } else if (reg < NUM_INTREGS) {
271 return reg;
272 } else {
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_MRM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/types.hh"
48
49class ThreadContext;
50class Checkpoint;
51class EventManager;
52
53namespace ArmISA
54{
55 class ISA
56 {
57 protected:
58 MiscReg miscRegs[NumMiscRegs];
59 const IntRegIndex *intRegMap;
60
61 void
62 updateRegMap(CPSR cpsr)
63 {
64 switch (cpsr.mode) {
65 case MODE_USER:
66 case MODE_SYSTEM:
67 intRegMap = IntRegUsrMap;
68 break;
69 case MODE_FIQ:
70 intRegMap = IntRegFiqMap;
71 break;
72 case MODE_IRQ:
73 intRegMap = IntRegIrqMap;
74 break;
75 case MODE_SVC:
76 intRegMap = IntRegSvcMap;
77 break;
78 case MODE_MON:
79 intRegMap = IntRegMonMap;
80 break;
81 case MODE_ABORT:
82 intRegMap = IntRegAbtMap;
83 break;
84 case MODE_UNDEFINED:
85 intRegMap = IntRegUndMap;
86 break;
87 default:
88 panic("Unrecognized mode setting in CPSR.\n");
89 }
90 }
91
92 public:
93 void clear()
94 {
95 memset(miscRegs, 0, sizeof(miscRegs));
96 CPSR cpsr = 0;
97 cpsr.mode = MODE_USER;
98 miscRegs[MISCREG_CPSR] = cpsr;
99 updateRegMap(cpsr);
100
101 SCTLR sctlr = 0;
102 sctlr.nmfi = 1;
103 sctlr.rao1 = 1;
104 sctlr.rao2 = 1;
105 sctlr.rao3 = 1;
106 sctlr.rao4 = 1;
107 miscRegs[MISCREG_SCTLR] = sctlr;
108
109 /*
110 * Technically this should be 0, but we don't support those
111 * settings.
112 */
113 miscRegs[MISCREG_CPACR] = 0x0fffffff;
114
115 /* One region, unified map. */
116 miscRegs[MISCREG_MPUIR] = 0x100;
117
118 /*
119 * Implemented = '5' from "M5",
120 * Variant = 0,
121 */
122 miscRegs[MISCREG_MIDR] =
123 (0x35 << 24) | //Implementor is '5' from "M5"
124 (0 << 20) | //Variant
125 (0xf << 16) | //Architecture from CPUID scheme
126 (0 << 4) | //Primary part number
127 (0 << 0) | //Revision
128 0;
129
130 //XXX We need to initialize the rest of the state.
131 }
132
133 MiscReg
134 readMiscRegNoEffect(int misc_reg)
135 {
136 assert(misc_reg < NumMiscRegs);
137 if (misc_reg == MISCREG_SPSR) {
138 CPSR cpsr = miscRegs[MISCREG_CPSR];
139 switch (cpsr.mode) {
140 case MODE_USER:
141 return miscRegs[MISCREG_SPSR];
142 case MODE_FIQ:
143 return miscRegs[MISCREG_SPSR_FIQ];
144 case MODE_IRQ:
145 return miscRegs[MISCREG_SPSR_IRQ];
146 case MODE_SVC:
147 return miscRegs[MISCREG_SPSR_SVC];
148 case MODE_MON:
149 return miscRegs[MISCREG_SPSR_MON];
150 case MODE_ABORT:
151 return miscRegs[MISCREG_SPSR_ABT];
152 case MODE_UNDEFINED:
153 return miscRegs[MISCREG_SPSR_UND];
154 default:
155 return miscRegs[MISCREG_SPSR];
156 }
157 }
158 return miscRegs[misc_reg];
159 }
160
161 MiscReg
162 readMiscReg(int misc_reg, ThreadContext *tc)
163 {
164 if (misc_reg == MISCREG_CPSR) {
165 CPSR cpsr = miscRegs[misc_reg];
166 Addr pc = tc->readPC();
167 if (pc & (ULL(1) << PcJBitShift))
168 cpsr.j = 1;
169 else
170 cpsr.j = 0;
171 if (pc & (ULL(1) << PcTBitShift))
172 cpsr.t = 1;
173 else
174 cpsr.t = 0;
175 return cpsr;
176 }
177 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
178 misc_reg < MISCREG_CP15_END) {
179 panic("Unimplemented CP15 register %s read.\n",
180 miscRegName[misc_reg]);
181 }
182 switch (misc_reg) {
183 case MISCREG_CLIDR:
184 warn("The clidr register always reports 0 caches.\n");
185 break;
186 case MISCREG_CCSIDR:
187 warn("The ccsidr register isn't implemented and "
188 "always reads as 0.\n");
189 break;
190 }
191 return readMiscRegNoEffect(misc_reg);
192 }
193
194 void
195 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
196 {
197 assert(misc_reg < NumMiscRegs);
198 if (misc_reg == MISCREG_SPSR) {
199 CPSR cpsr = miscRegs[MISCREG_CPSR];
200 switch (cpsr.mode) {
201 case MODE_USER:
202 miscRegs[MISCREG_SPSR] = val;
203 return;
204 case MODE_FIQ:
205 miscRegs[MISCREG_SPSR_FIQ] = val;
206 return;
207 case MODE_IRQ:
208 miscRegs[MISCREG_SPSR_IRQ] = val;
209 return;
210 case MODE_SVC:
211 miscRegs[MISCREG_SPSR_SVC] = val;
212 return;
213 case MODE_MON:
214 miscRegs[MISCREG_SPSR_MON] = val;
215 return;
216 case MODE_ABORT:
217 miscRegs[MISCREG_SPSR_ABT] = val;
218 return;
219 case MODE_UNDEFINED:
220 miscRegs[MISCREG_SPSR_UND] = val;
221 return;
222 default:
223 miscRegs[MISCREG_SPSR] = val;
224 return;
225 }
226 }
227 miscRegs[misc_reg] = val;
228 }
229
230 void
231 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
232 {
233 MiscReg newVal = val;
234 if (misc_reg == MISCREG_CPSR) {
235 updateRegMap(val);
236 CPSR cpsr = val;
237 Addr npc = tc->readNextPC() & ~PcModeMask;
238 if (cpsr.j)
239 npc = npc | (ULL(1) << PcJBitShift);
240 if (cpsr.t)
241 npc = npc | (ULL(1) << PcTBitShift);
242
243 tc->setNextPC(npc);
244 }
245 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
246 misc_reg < MISCREG_CP15_END) {
247 panic("Unimplemented CP15 register %s wrote with %#x.\n",
248 miscRegName[misc_reg], val);
249 }
250 switch (misc_reg) {
251 case MISCREG_CPACR:
252 newVal = bits(val, 27, 0);
253 if (newVal != 0x0fffffff) {
254 panic("Disabling coprocessors isn't implemented.\n");
255 }
256 break;
257 case MISCREG_CSSELR:
258 warn("The csselr register isn't implemented.\n");
259 break;
260 }
261 return setMiscRegNoEffect(misc_reg, newVal);
262 }
263
264 int
265 flattenIntIndex(int reg)
266 {
267 assert(reg >= 0);
268 if (reg < NUM_ARCH_INTREGS) {
269 return intRegMap[reg];
270 } else if (reg < NUM_INTREGS) {
271 return reg;
272 } else {
|