1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ARM_ISA_HH__
32#define __ARCH_MRM_ISA_HH__
33
34#include "arch/arm/registers.hh"
35#include "arch/arm/types.hh"
36
37class ThreadContext;
38class Checkpoint;
39class EventManager;
40
41namespace ArmISA
42{
43 class ISA
44 {
45 protected:
46 MiscReg miscRegs[NumMiscRegs];
47
48 public:
49 void clear()
50 {
51 memset(miscRegs, 0, sizeof(miscRegs));
52 CPSR cpsr = 0;
53 cpsr.mode = MODE_USER;
54 miscRegs[MISCREG_CPSR] = cpsr;
55 //XXX We need to initialize the rest of the state.
56 }
57
58 MiscReg
59 readMiscRegNoEffect(int misc_reg)
60 {
61 assert(misc_reg < NumMiscRegs);
62 return miscRegs[misc_reg];
63 }
64
65 MiscReg
66 readMiscReg(int misc_reg, ThreadContext *tc)
67 {
68 assert(misc_reg < NumMiscRegs);
69 return miscRegs[misc_reg];
70 }
71
72 void
73 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
74 {
75 assert(misc_reg < NumMiscRegs);
76 miscRegs[misc_reg] = val;
77 }
78
79 void
80 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
81 {
82 assert(misc_reg < NumMiscRegs);
83 miscRegs[misc_reg] = val;
84 }
85
86 int
87 flattenIntIndex(int reg)
88 {
89 return reg;
90 }
91
92 int
93 flattenFloatIndex(int reg)
94 {
95 return reg;
96 }
97
| 1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ARM_ISA_HH__
32#define __ARCH_MRM_ISA_HH__
33
34#include "arch/arm/registers.hh"
35#include "arch/arm/types.hh"
36
37class ThreadContext;
38class Checkpoint;
39class EventManager;
40
41namespace ArmISA
42{
43 class ISA
44 {
45 protected:
46 MiscReg miscRegs[NumMiscRegs];
47
48 public:
49 void clear()
50 {
51 memset(miscRegs, 0, sizeof(miscRegs));
52 CPSR cpsr = 0;
53 cpsr.mode = MODE_USER;
54 miscRegs[MISCREG_CPSR] = cpsr;
55 //XXX We need to initialize the rest of the state.
56 }
57
58 MiscReg
59 readMiscRegNoEffect(int misc_reg)
60 {
61 assert(misc_reg < NumMiscRegs);
62 return miscRegs[misc_reg];
63 }
64
65 MiscReg
66 readMiscReg(int misc_reg, ThreadContext *tc)
67 {
68 assert(misc_reg < NumMiscRegs);
69 return miscRegs[misc_reg];
70 }
71
72 void
73 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
74 {
75 assert(misc_reg < NumMiscRegs);
76 miscRegs[misc_reg] = val;
77 }
78
79 void
80 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
81 {
82 assert(misc_reg < NumMiscRegs);
83 miscRegs[misc_reg] = val;
84 }
85
86 int
87 flattenIntIndex(int reg)
88 {
89 return reg;
90 }
91
92 int
93 flattenFloatIndex(int reg)
94 {
95 return reg;
96 }
97
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