isa.hh (6745:cdc62b81747e) | isa.hh (7093:9832d4b070fc) |
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1/* | 1/* |
2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
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2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright --- 112 unchanged lines hidden (view full) --- 122 } 123 } 124 return miscRegs[misc_reg]; 125 } 126 127 MiscReg 128 readMiscReg(int misc_reg, ThreadContext *tc) 129 { | 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 112 unchanged lines hidden (view full) --- 134 } 135 } 136 return miscRegs[misc_reg]; 137 } 138 139 MiscReg 140 readMiscReg(int misc_reg, ThreadContext *tc) 141 { |
142 if (misc_reg == MISCREG_CPSR) { 143 CPSR cpsr = miscRegs[misc_reg]; 144 Addr pc = tc->readPC(); 145 if (pc & (ULL(1) << PcJBitShift)) 146 cpsr.j = 1; 147 else 148 cpsr.j = 0; 149 if (pc & (ULL(1) << PcTBitShift)) 150 cpsr.t = 1; 151 else 152 cpsr.t = 0; 153 return cpsr; 154 } |
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130 return readMiscRegNoEffect(misc_reg); 131 } 132 133 void 134 setMiscRegNoEffect(int misc_reg, const MiscReg &val) 135 { 136 assert(misc_reg < NumMiscRegs); 137 if (misc_reg == MISCREG_SPSR) { --- 28 unchanged lines hidden (view full) --- 166 miscRegs[misc_reg] = val; 167 } 168 169 void 170 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 171 { 172 if (misc_reg == MISCREG_CPSR) { 173 updateRegMap(val); | 155 return readMiscRegNoEffect(misc_reg); 156 } 157 158 void 159 setMiscRegNoEffect(int misc_reg, const MiscReg &val) 160 { 161 assert(misc_reg < NumMiscRegs); 162 if (misc_reg == MISCREG_SPSR) { --- 28 unchanged lines hidden (view full) --- 191 miscRegs[misc_reg] = val; 192 } 193 194 void 195 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 196 { 197 if (misc_reg == MISCREG_CPSR) { 198 updateRegMap(val); |
199 CPSR cpsr = val; 200 Addr npc = tc->readNextPC() & ~PcModeMask; 201 if (cpsr.j) 202 npc = npc | (ULL(1) << PcJBitShift); 203 if (cpsr.t) 204 npc = npc | (ULL(1) << PcTBitShift); 205 206 tc->setNextPC(npc); |
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174 } 175 return setMiscRegNoEffect(misc_reg, val); 176 } 177 178 int 179 flattenIntIndex(int reg) 180 { 181 assert(reg >= 0); --- 31 unchanged lines hidden --- | 207 } 208 return setMiscRegNoEffect(misc_reg, val); 209 } 210 211 int 212 flattenIntIndex(int reg) 213 { 214 assert(reg >= 0); --- 31 unchanged lines hidden --- |