isa.hh (14133:f3e7e7c3803d) | isa.hh (14242:076b215de8d4) |
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1/* 2 * Copyright (c) 2010, 2012-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 169 unchanged lines hidden (view full) --- 178 chain mutex(bool v = true) const { 179 info[MISCREG_MUTEX] = v; 180 return *this; 181 } 182 chain banked(bool v = true) const { 183 info[MISCREG_BANKED] = v; 184 return *this; 185 } | 1/* 2 * Copyright (c) 2010, 2012-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 169 unchanged lines hidden (view full) --- 178 chain mutex(bool v = true) const { 179 info[MISCREG_MUTEX] = v; 180 return *this; 181 } 182 chain banked(bool v = true) const { 183 info[MISCREG_BANKED] = v; 184 return *this; 185 } |
186 chain banked64(bool v = true) const { 187 info[MISCREG_BANKED64] = v; 188 return *this; 189 } |
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186 chain bankedChild(bool v = true) const { 187 info[MISCREG_BANKED_CHILD] = v; 188 return *this; 189 } 190 chain userNonSecureRead(bool v = true) const { 191 info[MISCREG_USR_NS_RD] = v; 192 return *this; 193 } --- 443 unchanged lines hidden (view full) --- 637 break; 638 } 639 } else { 640 if (miscRegInfo[reg][MISCREG_BANKED]) { 641 bool secureReg = haveSecurity && !highestELIs64 && 642 inSecureState(miscRegs[MISCREG_SCR], 643 miscRegs[MISCREG_CPSR]); 644 flat_idx += secureReg ? 2 : 1; | 190 chain bankedChild(bool v = true) const { 191 info[MISCREG_BANKED_CHILD] = v; 192 return *this; 193 } 194 chain userNonSecureRead(bool v = true) const { 195 info[MISCREG_USR_NS_RD] = v; 196 return *this; 197 } --- 443 unchanged lines hidden (view full) --- 641 break; 642 } 643 } else { 644 if (miscRegInfo[reg][MISCREG_BANKED]) { 645 bool secureReg = haveSecurity && !highestELIs64 && 646 inSecureState(miscRegs[MISCREG_SCR], 647 miscRegs[MISCREG_CPSR]); 648 flat_idx += secureReg ? 2 : 1; |
649 } else { 650 flat_idx = snsBankedIndex64((MiscRegIndex)reg, 651 !inSecureState(miscRegs[MISCREG_SCR], 652 miscRegs[MISCREG_CPSR])); |
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645 } 646 } 647 return flat_idx; 648 } 649 | 653 } 654 } 655 return flat_idx; 656 } 657 |
658 int 659 snsBankedIndex64(MiscRegIndex reg, bool ns) const 660 { 661 int reg_as_int = static_cast<int>(reg); 662 if (miscRegInfo[reg][MISCREG_BANKED64]) { 663 reg_as_int += (haveSecurity && !ns) ? 2 : 1; 664 } 665 return reg_as_int; 666 } 667 |
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650 std::pair<int,int> getMiscIndices(int misc_reg) const 651 { 652 // Note: indexes of AArch64 registers are left unchanged 653 int flat_idx = flattenMiscIndex(misc_reg); 654 655 if (lookUpMiscReg[flat_idx].lower == 0) { 656 return std::make_pair(flat_idx, 0); 657 } --- 113 unchanged lines hidden --- | 668 std::pair<int,int> getMiscIndices(int misc_reg) const 669 { 670 // Note: indexes of AArch64 registers are left unchanged 671 int flat_idx = flattenMiscIndex(misc_reg); 672 673 if (lookUpMiscReg[flat_idx].lower == 0) { 674 return std::make_pair(flat_idx, 0); 675 } --- 113 unchanged lines hidden --- |